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5.3.10.3
Reading from
the
Bus
5.3.10.3.1
When
the
interface
is
addressed
to
listen,
the
GPIA
conducts
the
handshake procedure up
to
the point
where
the ready
for
data
(RFD)
indication
is
given.
At
this point
IC12-27
is
at
logic
0,
giving a logic
1
level
at
IC18-11.
This
puts three of
the
bilateral
switches
of
IC13
into
the conducting
state,
thus
completing
the
RFD
line.
The
logic
0
at
IC12-27
also
puts the buffers
in
IC14 and IC15
into the receive condition.
Data from
the bus enters the
GPIA
data-in register
and IC12-40 goes
to logic
0
providing
an interrupt request
to
the
microprocessor
IC9.
5.3.10.3.2
The
microprocessor
interrupt
routine
establishes
the
reason
for
the
interrupt.
The
address decoder
IC8
is
enabled
via
IC27-15, IC26-8,
and A7. The decoder
is
addressed
using
lines
GA4,
5,
and
6,
and
gives
the
GPIA
enable
signal at
IC8-15.
The
data-in
register of the
GPIA
is
addressed
using the
R/W
line
and
lines
AO,
1,
and
2.
The
microprocessor then
reads the
contents
of
the data-in register
and
transfers the
data
to
memory.
5.3.10.3.3
When
the
data-in
register
has
been
read, the
GPIA
cancels
the interrupt
request and allows
the
data
accepted
(DAC)
line
to
go
high.
The
handshake
routine
then
continues,
and
a further byte,
if
available
is
loaded
into
the data-in
register.
The
interrupt and
data
transfer
sequence
is
then repeated.
5.3.10.4
Writing
to the
Bus
5.3.10.4.1
When
the
GPIA
is
addressed
to
talk,
its
internal
data-out
register
will
normally
be
empty.
Under
these conditions IC12-40 goes
to logic
0
and
provides
an
interrupt request
to the
microprocessor.
5.3.10.4.2
IC17B
is
in
the reset
state,
giving a
logic
1
at
IC18-12.
Since
IC12-27
is
at logic
1
when
the
GPIA
is
addressed
to talk,
IC18-13
is
also
at logic
1.
The
resulting
logic
0
at
IC18-11 opens
three
circuits of bilateral
switches
in
IC13
to
break
the
RFD
line.
The
fourth
bilateral
switch
conducts,
due
to
the
logic
1
at
IC19-1G, and
holds
IC12-18
at
0V.
Even
if
the listening
device
asserts that
it is
ready
for
data,
IC12
will
not
attempt
to
load the contents of the data-out
register
onto the
bus.
5.3.10.4.3
The
microprocessor
interrupt
routine
establishes
the
reason
for
the
interrupt.
The
microprocessor then enables
the address
decoder, IC8,
via
IC27-15,
IC26-8, and
A7. The decoder
is
addressed
using
lines
GA4,
5,
and
6,
and
gives the
GPIA
enable
signal
at
IC8-15.
The
data-K>ut register of
the
GPIA
is
addressed
using the
R/W
line
and
lines
GAO,
1
and
2,
and a data byte
is
written into the
register.
The
GPIA
then
cancels the
interrupt request.
5.3.10.4.4
Following the
data
transfer, the
microprocessor
sets
IC17B,
using
line
PB7,
to give
a
logic
0
at
IC18-12.
This gives a
logic
1
at
IC18-11,
which
enables three
bilateral
switches
in
IC13 and connects
the
RFD
line.
The
fourth
switch
in
IC13
is
disabled,
thereby
releasing
IC12-18 from
0V.
When
the listening
device
asserts that
it
is
ready
for
data,
the
GPIA
loads the contents of the data-out register
onto
the bus
and
continues with the
handshake
routine.
5.3.10.4.5
When
the
data-out
register
has
been
read, the
GPIA
generates
a further
interrupt request.
The microprocessor
resets
IC17B,
using
line
PBS,
giving
a
logic
1
at
IC18-12
so that the
RFD
line
is
again
broken
at
IC13.
The
data
transfer
and data
transmission
sequence
is
then repeated.
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