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5.3.3.2.3
Reference Frequency
5. 3. 3. 2.
3.1
The
internal
reference
signal
is
applied
to
IC39-2 and
the
external
reference
signal,
if
present, to IC39-3.
A
buffered
version of the
external reference
is
present
at
IC39-24 and
is
applied
to
the
detector D26, C96, and R129.
The
detector
output
is
fed
to
IC23-6 and
is
read periodically by the microprocessor.
If
the
level
is
above
the
TTL
logic
1
threshold, the
microprocessor
sets
IC39-38
to
logic
0
and
the
measurement
block switches
to
use the external reference.
5.3.3. 2.3.2
A
10
MHz
signal,
derived
from
the frequency standard,
is
present
at
IC39-
37 and
is
fed
to
the
10.
MHz
STD
OUTPUT
socket on
the rear panel
via
PL19
pin
2.
5. 3. 3. 2. 3.
3
A
10
MHz
reference
signal,
derived
from
the
frequency standard,
is
present
at
IC39-36.
This
signal
is
applied
to
the
TEC,
HI,
at pin
6,
and, after inversion
in
IC29e,
to
IC18-24.
5.3.
3.
2.4
Microprocessor Clock and
Timer
5.3.3.
2. 4.1
A
5
MHz
clock
signal
for
the
microprocessor
(and
the
GPIB
microprocessor
if
fitted)
is
taken
from
IC18-2.
A
39.0625
kHz
clock
signal for the
microprocessor timer
is
taken
from
IC18-4.
5.3.3.2.5
Channel
C
Gate and Reset
5.3.
3.
2.5.1
A GATE
signal (logic
0
during the
measurement
period)
and
a
RESET
signal
(negative-going
pulse at the
end
of
each measurement
period)
are
taken
from
IC39-27 and IC18-40 and fed
to the
Channel
C
block
via
PL7
pins 17
and
15.
5.3.3.2.6
External
Arming
Input
5. 3. 3.
2.6.1
Signal
connected
to the
EXT
ARM
INPUT
socket on the rear panel are fed
to
IC18-27
via
PL19
pin
1
and
the amplifier
stage Q5.
5.3.3.2.7
Control
Signals
5. 3. 3. 2.
7.1
The
logic levels
on
lines
Q0
to
Q4, between IC18 and IC39
are
shown
in
Table
5.1.
These
levels
are stable
if
the following conditions
exist:
a.
No
signals
are applied to
any
of the channel
inputs
b.
Auto-trigger
is
disabled
on Channels
A
and B
5-9
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