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5. 3.
6.2
Circuit Description
5. 3.
6.
2.1
The schematic
is
given on page
7-11.
The microprocessor
clock
and
timer
signals
are
generated
in
the
measurement
block
and
are fed to
IC19-39 and
IC19-37.
A
RESET
signal
is
generated
in
the
standby and
IRQ
block
when
the
instrument
is
switched
on
or off
and
is
fed
to
IC19-1.
5. 3.
6.
2. 2
The
microprocessor bus
for the
high-order address
bits
is
designated
A8
to
A12.
The
multiplexed
bus,
used
for
the low-order address
bits
and
for
data
is
designated
BO
to
B7.
The
microprocessor
also
has
two
input/output ports
PAO
to
PA7
and PBO
to
PB7.
5.3.6.
2.3
Multiplexed Bus
Operation
5. 3.
6.2.
3.1
The
microprocessor puts IC19-6
(ADDRESS STROBE)
at
logic
1
and
(DATA STROBE)
at
logic
0.
This enables the address latch
IC20
(IC2Q-11
at logic
1),
disables
ROM
IC22 (IC22-20
at logic
1),
and
disables the
address
decoder IC21
(IC21-6)
at
logic
0).
5. 3.
6. 2.
3.
2
This address
is
put
onto
lines
BO
to
B7 and
A8
to
A12.
When
the
lines
have
settled,
the
ADDRESS STROBE
line
is
taken
to logic
0.
The
low-order
bits
of
the address
are
latched
into
IC20 and
are held
on
address
lines
AO
to
A7.
Lines BO to
B7
are
now
free for use
as
a data
bus.
5.3.6.
2.4
Address Decoding
5.3.6.
2.4.1
The
levels
on address
lines
A6
to
A12
are
decoded
in
IC21
to
provide
the
following outputs:
a.
MCC
SEL,
the chip-select signal
for
IC18
b.
GPIB
SEL,
the chip-select
for
the
GPIB
address
decoder
c.
WR,
the
write control
signal for
H2
d.
Y6,
the chip select signal
for
output
latch
IC25
e.
Y7,
the
chip select signal
for
output
latch
IC24
5.
3. 6.
2.4.2
These
outputs are only available
when
IC21
is
enabled by
a
logic
1
at
IC21-6
and
a
logic
0
at
IC21-4,5.
The
level
at
IC21-6
is
set
by the
DATA
STROBE
output
at
IC19-4,
which
is
at
logic
1
when
the multiplexed
bus
is
available for
data
transfer.
All
outputs
from
IC21 are decoded
from
addresses with
lines
A9
to
A12
at logic
0
when
IC21-
4, 5
are held
at logic
0
by
the
output
from
IC27a,
b,
and
d.
5.3.6. 2.5
Input
and Output
Latches
5. 3.
6.2. 5.1
The
logic levels
required on the instrument control
lines
and on
the
PAGE
line
(most
significant
bit
of
RAM
address) are set
into
the
output latches
IC24 and
IC25
from data
port
B
of
the
microprocessor.
The
latch strobe signals
are
decoded
in
IC21.
Data
may
be read by
the
microprocessor from the
input latch
IC23.
The
latch strobe
signal
is
provided
via
data
port
A
of the
microprocessor.
5-15
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