Stanford Research Systems DS360 Operating Manual And Programming Reference page 124

7-4 Circuit Description
main processor (from U416). U102, U103 and U104 are independent oscillators that
clock the CS8402. Only one is active at a time and is selected by U205 (74HC153).
The digital audio signals are output on three different connectors. J201 is an S/PDIF,
coax (RCA connector), U206 is an S/PDIF fiber optic connector and J207 is an AES-
EBU XLR connector. The outputs on the "wire" connectors are transformer isolated
from the digital board.
J206 contains the control signals to and from the analog board. These include a three wire
serial interface to control relays and DAC's, burst control signals and the sync signal.
J203, J204 and J205 are auxiliary output signals; J202 is the external trigger input.
Burst Control
U301 and U302 are PAL's that generates the rate and width clocking signals for the
synchronous bursts. U303 (8254) is a triple 16 bit counter used to generate burst rates,
burst widths and clocking for noise signals. U306 and U307 (74HC74) are used to
synchronize external events to the burst clock. U308 contains all of the processor control
signals for bursts.
Microprocessor and System Clocks
U401 is a Z80 general purpose microprocessor. It is clocked at 10.6 MHz, generated from
the main system clock. The 16 bit address space (A0-A15), is divided into ROM (U402)
and RAM (U403) by U413. The memory map for ROM and RAM is as follows:
U407 (74HC154) generates all chip selects for the system. U404 and U406 are system
status and control ports, respectively. U416 is the digital output control port (for U201).
U415-A or's together all of interrupt signals to generate the maskable interrupt to the
Z80.
U405 (8254) is a triple 16 bit counter, used to generate the real time clock (1.67 ms), set
the RS232 baud rate (for U604) and speaker tones (for SP401). The baud rate can range
from 300 to 19.2k baud. D401, D402, and BT101 provide the battery backup to the
system RAM (U403). Q402, Q403 and associated resistors and capacitors generate the
power on reset and power fail shut down.
U408 is a 32.333 MHz 25 ppm oscillator. It is buffered by U411 to three different paths,
the system clocks, DSP control logic and D/A sync control. This is to avoid any signal
contamination due to reflections or load variations. The main clock is divided down by
U409 and U410 to provide the different system clocks.
DS360 Ultra Low Distortion Function Generator
ROM $0000 to $CFFF
RAM $D000 to $FFFF