Stanford Research Systems DS360 Operating Manual And Programming Reference page 123

Overview
The DS360's circuitry is divided into two major sections: the digital section and the
analog section. The digital section contains the controlling microprocessor,
communications interfaces, front panel control and digital signal processor. The analog
section contains the analog to digital converter, waveform conditioning circuitry,
amplifiers and attenuators. In addition there are four other boards: the front panel display
board, the front panel output board and two switchable resistor boards.
Digital Board
This section covers schematics DIG-1 through DIG-7 at the end of this section.
The digital board contains the main CPU, system memory, external interfaces including
the front panel, RS-232 and GPIB, the digital signal processor and its memory, timing
and control logic and the digital power supply.
DSP and Control Logic
U101 is a Motorola DSP56002FC40, a 24 bit fixed point, digital signal processor. It is
capable of performing a multiply and two register moves in a single 53 ns cycle. The
DSP56002 has 512 words of internal data RAM, and 512 words of program RAM. There
is also two internal ROM tables, a 256 word sine table and a 256 word A/Mu Law table
(not used in the DS360). There is a single external data bus, which is multiplexed into
three sections, X and Y data memory and P program memory. U102, U103 and U104
(32k * 8) make up the DSP memory. U114 segments the memory into the X, Y, and P
sections.
The DSP56002 contains an internal PLL (phase lock loop) that multiplies the system
clock (see DIG-4) of 5.3 MHz up to 18.9 MHz internally. Communications with the main
processor take place via the Host Port (U101 H0-H7, HA0-HA2, HR/W, HEN).
Data is sent from the DSP to the D/A converter through parallel to serial converters
(U105-U107) (74HC597), on the DSP memory bus. These signals are synchronized to
the system clock before passing to the analog board through J101. U111 and U112
generate the data clocking and frame sync signals.
U109 generates output control signals from the DSP data and address lines. U115 and
U116 synchronize status information to the output data. U110 generates clocking and
sync signals for the digital output. Communications between the DSP56002 and digital
output are via the serial output (STD, SCK) and the U108 port.
Digital Outout, I/O
The CS8402 (U201) is a digital audio transmitter, capable of outputting data in both
AES-EBU and S/PDIF formats. The DSP (U101) and clocking logic calculates output
values and transmits them to the CS8402 over a 3 wire serial interface (data, clock &
sync). Auxiliary control signals are received from both the DSP (from U108) and the
Circuit Description
DS360 Ultra Low Distortion Function Generator
7-3