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Freescale Semiconductor MPC5633M Manual

Freescale Semiconductor MPC5633M Manual (1384 pages)

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 10 MB

Table of Contents

Table of Contents
3
The MPC563XM Microcontroller Family
23
MPC563XM Blocks
24
Chapter 1 Block Summary

25
- MPC563XM Features
  26
  - E200Z335 Core
    35
  - Crossbar
    37
Chapter 14 Interrupt Controller

38
- Fmpll
  39
- Calibration EBI
  40
- Ecsm
  41
Chapter 11

42
- Flash
  42
- Sram
  43
- Etpu
  44
- Eqadc
  46
- Dspi
  48
- Esci
  50
- Flexcan
  51
- System Timers
  52
Chapter 20 Software Watchdog Timer (SWT)

53
Chapter 31 JTAG

55
- Introduction
  57
- Device Pin Assignments
  63
Chapter 2 Ballmap: 208 MAPBGA

65
- External Signal Summary
  66
- Detailed Signal Descriptions
  76
Chapter 32 Nexus Port Controller (NPC)

78
- Jtag
  79
- Flexcan
  80
- Dspi
  81
- Eqadc
  82
- Etpu
  85
- Emios
  88
- Clock Synthesizer
  89
- Power / Ground
  90
Chapter 4

93
- Reset Sources
  93
- Reset Vector
  94
- Clock Quality Monitor Gating Signal
  95
  - Power-On Reset
    98
  - Loss of Clock
    99
  - Checkstop Reset
    100
  - Software External Reset
    101
  - Reset Configuration Timing
    103
  - Reset Weak Pull Up/Down Configuration
    104
  - Overview
    105
Chapter 5

106
- Modes and Clock Architecture
  106
  - Clock Architecture
    110
  - Introduction
    115
Chapter 6 Location of Detailed Documentation

116
- Information Specific to this Device
  117
- Introduction
  118
- Overview
  119
- Features
  120
- Memory Map/Register Definition
  125
- Register Descriptions
  127
- Functional Description
  151
Chapter 7

152
- DMA Basic Data Flow
  152
- DMA Performance
  155
- Initialization/Application Information
  158
- DMA Programming Errors
  159
- DMA Arbitration Mode Considerations
  160
- DMA Transfer
  161
- TCD Status
  164
- Channel Linking
  165
- Dynamic Programming
  166
- Hardware Request Release Timing
  167
- Information Specific to this Device
  169
- Device-Specific Register Information
  170
  - Introduction
    171
  - Features
    173
- XBAR Registers
  174
  - XBAR Register Descriptions
    177
  - Coherency
    185
  - Priority Assignment
    187
  - Master Port Functionality
    188
  - Slave Port Functionality
    191
    
    Initialization/Application Information
    198
    
    Overview
    199
  - Slave Ports
    200
Chapter 9

201
- PBRIDGE Features
  201
- PBRIDGE Functional Description
  202
  - Introduction
    203
  - Modes of Operation
    204
  - Memory Map and Register Definition
    208
Chapter 10

209
- C90FL Register Descriptions
  209
- Flash Memory Block (C90FL)
  214
- C90FL Block Features
  215
- C90FL Modes of Operation
  216
- C90FL Flash EEPROM Functional Description
  217
- C90FL Memory Map and Register Definition
  219
  - Introduction
    243
  - Features
    244
  - Modes of Operation
    245
  - Register Descriptions
    248
  - Functional Description
    279
- Access Protections
  280
- Access Pipelining
  281
- Read-While-Write Functionality
  283
- Wait-State Emulation
  284
- Flash Memory Array: User Mode
  285
  - Overview
    299
  - Functional Description
    300
Chapter 18

301
- Module Memory Map
  301
  - Information Specific to this Device
    303
  - Overview
    304
  - Features
    305
  - External Signal Description
    308
  - Signal Function/Direction by Mode
    313
  - Signal Output Buffer Enable Logic by Mode
    314
    
    Memory Map/Register Definition
    315
    
    Register Descriptions
    316
    
    Functional Description
    324
  - External Bus Operations
    330
  - Initialization/Application Information
    397
  - Running with Asynchronous Memories
    398
  - Connecting an MCU to Multiple Memories
    400
  - Address Decoding Example for External Master Accesses
    401
  - EBI Operation with Reduced Pinout Mcus
    402
  - Address/Data Multiplexing Connection Examples
    404
  - Summary of Differences from Mpc5Xx
    408
    
    Information Specific to this Device
    411
    
    Block Diagram
    412
    
    Features
    413
    
    Modes of Operation
    414
    
    Debug Mode
    415
    
    External Signal Description
    416
  - INTC Block Configuration Register (INTC_BCR)
    417
  - INTC Current Priority Register for Processor 0 (INTC_CPR_PRC0)
    418
  - INTC Current Priority Register for Processor 1 (INTC_CPR_PRC1)
    419
  - INTC Interrupt Acknowledge Register for Processor 0 (INTC_IACKR_PRC0)
    420
  - INTC Interrupt Acknowledge Register for Processor 1 (INTC_IACKR_PRC1)
    421
  - INTC End of Interrupt Register for Processor 1 (INTC_EOIR_PRC1)
    422
  - Functional Description
    425
  - Priority Management
    426
  - Handshaking with Processor
    428
  - Reserved Spaces in Memory Map
    431
  - Initialization/Application Information
    432
  - Code Compression's Impact on Vector Table
    434
  - Priority Ceiling Protocol
    435
  - Selecting Priorities According to Request Rates and Deadlines
    436
  - Software Setable Interrupt Requests
    437
  - Lowering Priority Within an ISR
    438
  - Examining LIFO Contents
    439
  - Introduction
    441
Chapter 15

443
- Critical Input
  443
  - Overview
    465
  - Modes of Operation
    466
- Signal Description
  467
Chapter 29

473
- Memory Map
  473
- Siu_Base
  475
- MCU ID Register 2 (SIU_MIDR2)
  475
  - Register Descriptions
    475
  - MCU ID Register (SIU_MIDR)
    477
- Reset Status Register (SIU_RSR)
  478
- System Reset Control Register (SIU_SRCR)
  480
- External Interrupt Status Register (SIU_EISR)
  481
- Dma/Interrupt Request Enable Register (SIU_DIRER)
  482
- Dma/Interrupt Request Select Register (SIU_DIRSR)
  483
- Overrun Status Register (SIU_OSR)
  484
- Overrun Request Enable Register (SIU_ORER)
  484
- IRQ Rising-Edge Event Enable Register (SIU_IREER)
  485
- External IRQ Digital Filter Register (SIU_IDFR)
  486
- Pad Configuration Registers (SIU_PCR)
  487
- GPO Data Output Registers (SIU_GPDO350 - SIU_GPDO413)
  534
- Eqadc Trigger Input Select Register (SIU_ETISR)
  536
- External IRQ Input Select Register (SIU_EIISR)
  538
- DSPI Input Select Register (SIU_DISR)
  542
- MUX Select Register 3 (SIU_ISEL3)
  545
- Chip Configuration Register (SIU_CCR)
  546
- External Clock Control Register (SIU_ECCR)
  547
- Compare a High Register
  548
- Compare B High Register
  549
- System Clock Register (SIU_SYSDIV)
  550
- Halt Register (SIU_HLT)
  551
- Halt Acknowledge Register (SIU_HLTACK)
  552
  - Information Specific to this Device
    555
  - Features
    556
  - Modes of Operation
    557
  - External Signal Description
    558
  - Memory Map and Register Definition
    559
  - Register Descriptions
    560
  - Functional Description
    569
Chapter 17

570
- Lock Detection
  570
- Frequency Modulation
  574
- Overview
  577
- Register Descriptions
  578
- Information Specific to this Device
  591
- Memory Map and Register Definition
  592
  - Functional Description
    596
  - Information Specific to this Device
    597
Chapter 8

598
- Introduction
  598
- Memory Map
  599
  - Functional Description
    604
  - Overview
    607
  - Internal Boot Mode
    608
  - BAM Program Operation
    609
  - Reset Configuration Half Word (RCHW)
    611
Chapter 21

613
- Internal Boot Mode
  613
- Serial Boot Mode
  614
- Booting from the Calibration Bus
  620
- Information Specific to this Device
  623
Chapter 22

625
- Device-Specific Register Information
  625
- Introduction
  626
  - Overview
    627
- External Signal Description
  628
- Memory Map/Register Definition
  629
  - Register Descriptions
    631
  - Functional Description
    654
  - Unified Channel (UC)
    657
  - Wheel Speed Channel (WSC)
    703
  - IP Bus Interface Unit (BIU)
    710
  - Red Line Client Submodule (REDC)
    711
    
    Initialization/Application Information
    712
    
    Introduction
    717
  - Overview
    718
  - Features
    723
Chapter 27

727
- Modes of Operation
  727
- External Signal Description
  729
  - Detailed Signal Descriptions
    730
  - Memory Map/Register Definition
    731
Chapter 23

735
- System Configuration Registers
  735
- Time Base Registers
  745
- Engine Related Registers
  750
- Channel Registers Layout
  752
- Global Channel Registers
  753
- Channel Configuration and Control Registers
  760
- Functional Description
  766
- Host Interface
  781
- Scheduler
  787
- Parameter Sharing and Coherency
  794
- Enhanced Channels
  798
- Time Bases
  842
- EAC - Etpu Angle Counter
  849
- Microengine
  868
- Microinstruction Set
  885
- Test and Development Support
  917
- Initialization/Application Information
  924
  - Reset Options
    925
  - Multiple Parameter Coherency Methods
    926
  - Programming Hints and Caveats
    927
  - Estimating Worst Case Latency
    928
  - Endianness
    944
  - Initialization Code Example
    949
  - Predefined Channel Mode Summary
    952
  - MISC Algorithm
    955
- Information Specific to this Device
  957
- Introduction
  958
Chapter 30 Block Diagram

959
- Features
  960
- Modes of Operation
  962
Chapter 24

963
- Debug Mode
  963
- Stop Mode
  964
- Factory Test Mode
  965
- Detailed Signal Descriptions
  968
- Memory Map/Register Definition
  971
  - EQADC Register Descriptions
    973
  - On-Chip ADC Registers
    1004
- Functional Description
  1015
  - Data Flow in EQADC
    1016
  - Command/Result Queues
    1032
  - EQADC Result Fifos
    1061
  - On-Chip ADC Configuration and Control
    1065
  - Internal/External Multiplexing
    1074
  - EQADC Dma/Interrupt Request
    1080
  - EQADC Synchronous Serial Interface (SSI) Sub-Block
    1083
  - EQADC Parallel Side Interface (PSI) Sub-Block
    1088
  - Analog Sub-Block
    1091
  - Supported EQADC Configurations
    1095
- Initialization/Application Information
  1097
  - EQADC/DMAC Interface
    1101
  - Sending Immediate Command Setup Example
    1103
  - Modifying Queues
    1104
  - Cqueue and Rqueues Usage
    1105
  - ADC Result Calibration
    1107
  - EQADC Versus QADC
    1109
- Information Specific to this Device
  1115
  - Features
    1116
  - Modes of Operation
    1117
Chapter 25

1119
- Decimation Filter Registers Description
  1119
- Decimation Filter Memory Map for Parallel Side Interface
  1127
- Functional Description
  1129
  - Input Buffer Description
    1131
  - Output Buffer Description
    1132
  - Bypass Configuration Description
    1133
  - IIR and FIR Filter
    1134
  - Filter Prefill Control Description
    1137
  - Timestamp Data Transmission
    1138
  - Interrupt Request Description
    1139
- Initialization Information
  1140
- Filter Example Simulation
  1141
  - Input Data Calculation
    1142
  - Filter Results
    1143
    
    Information Specific to this Device
    1145
    
    Overview
    1146
    
    Features
    1147
Chapter 26

1148
- DSPI Configurations
  1148
  - Modes of Operation
    1149
  - External Signal Description
    1150
- Detailed Signal Description
  1151
- Memory Map and Register Definition
  1152
  - Register Descriptions
    1153
  - Functional Description
    1175
  - Modes of Operation
    1176
  - Start and Stop of DSPI Transfers
    1178
  - Serial Peripheral Interface (SPI) Configuration
    1179
  - Deserial Serial Interface (DSI) Configuration
    1182
  - Combined Serial Interface (CSI) Configuration
    1187
  - DSPI Baud Rate and Clock Delay Generation
    1190
  - Transfer Formats
    1193
  - Continuous Serial Communications Clock
    1200
  - Timed Serial Bus (TSB)
    1201
  - Interrupts/Dma Requests
    1204
  - Power Saving Features
    1206
  - Initialization/Application Information
    1207
  - Baud Rate Settings
    1208
  - Delay Settings
    1209
  - Calculation of FIFO Pointer Addresses
    1210
    
    Introduction
    1213
    
    Overview
    1214
    
    Modes of Operation
    1215
    
    External Signal Description
    1216
    
    Register Descriptions
    1218
    
    Functional Description
    1234
  - Baud Rate and Clock Generation
    1237
  - Baud Rate Tolerance
    1239
  - SCI Mode
    1241
  - LIN Mode
    1256
    
    Interrupts
    1264
    
    Application Information
    1265
    
    Information Specific to this Device
    1267
    
    Overview
    1268
Chapter 28

1269
- Flexcan Module Features
  1269
  - Modes of Operation
    1270
  - External Signal Description
    1271
- Flexcan Memory Mapping
  1272
- Message Buffer Structure
  1273
- Rx FIFO Structure
  1277
  - Register Descriptions
    1278
  - Functional Description
    1297
- Transmit Process
  1298
- Arbitration Process
  1299
- Matching Process
  1301
- Data Coherence
  1302
- Rx FIFO
  1305
- Modes of Operation Details
  1310
- Interrupts
  1313
- Initialization/Application Information
  1314
- Flexcan Addressing and RAM Size Configurations
  1315
- Information Specific to this Device
  1317
- Overview
  1318
- Modes of Operation
  1319
Chapter 19

1320
- Register Descriptions
  1320
- Functional Description
  1325
- Interrupts
  1326
- Initialization and Application Information
  1327
- Introduction
  1329
Chapter 12

1330
- Block Diagram
  1330
  - External Signal Description
    1331
  - Memory Map/Register Definition
    1332
  - Trimming Register (TRIMR)
    1334
  - Status Register (SR)
    1337
  - Functional Description
    1340
  - V Lvi
    1341
  - V Lvi
    1343
  - V Lvi
    1344
- Application Information
  1347
  - Information Specific to this Device
    1349
  - Auxiliary TAP Controller Instructions
    1350
    
    Features
    1351
    
    External Signal Description
    1352
- Register Definition
  1353
  - Functional Description
    1356
  - JTAGC Block Instructions
    1358
  - Boundary Scan
    1360
  - Information Specific to this Device
    1363
  - Available Features
    1364
  - Features
    1365
  - Device-Specific Parameters
    1366
  - External Signal Description
    1367
- Register Definition
  1368
  - Register Descriptions
    1369
  - Functional Description
    1373
  - Ieee 1149.1-2001 (Jtag) Tap
    1376
  - Nexus JTAG Port Sharing
    1380
  - Initialization/Application Information
    1381

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