Sharp PC-4741 Service Manual page 56

RQ/GT1
1/0
QS1,QSO I
INT
0
BUSY
0
READY I
RESET I
ClK
I
Vee
GND
Table 1. 8087 Pin Description (Continued)
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P C-4741
REQUEST/GRANT: This request/grant pin is used by another local bus master to force the 8087
to request the local bus. If the 8087 is not in control of the bus when the request is made the
request/grant sequence is passed through the 8087 on the RQ/GTO pin one cycle later. Sub-
sequent grant and release pulses are also passed through the 8087 with a two and one clock
delay, respectively, for resynchronization. RQ/GT1 has an internal pullup resistor, and so may
be left unconnected. If the 8087 has control of the bus the request/grant sequence is as follows:
1. A pulse 1 ClK wide from another local bus master indicates a local bus request to the 8087
(pulse 1).
2. During the 8087's next T4 or Tl a pulse 1 ClK wide from the 8087 to the requesting master
(pulse 2) indicates that the 8087 has allowed the local bus to float and that it will enter the
"RQ/GT
acknowledge" state at the next ClK. The 8087's control unit is disconnected logically
from the local bus during "RQ/GT acknowledge."
3. A pulse 1 ClK wide from the requesting master indicates to the 8087 (pulse 3) that the
"RQ/GT" request is about to end and that the 8087 can reclaim the local bus at the next ClK.
Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one
dead ClK cycle after each bus exchange. Pulses are active lOW.
For 80186/80188 system, the RQ/GT1 line may be connected to the 82188 Integrated Bus
Controller. In this case, a third processor with a HOLD, HlDA bus exchange system may
acquire the bus from the 8087. For this configuration, RQ/GT1 will only be used if the 8087 is the
bus master. Refer to 82188 data sheet for further information.
QS1, QSO: QS1 and QSO provide the 8087 with status to allow tracking of the CPU instruction
queue.
QS1 QSO
o
(lOW)
0
No Operation
0 1 First Byte of Op Code from Queue
1 (HIGH) 0 Empty the Queue
1 1 Subsequent byte from Queue
INTERRUPT: This line is used to indicate that an unmasked exception has occurred during
numeric instruction execution when 8087 interrupts are enabled. This signal is typically routed to
an 8259A for
8086/8088
systems and to INTO for
80186/80188
systems. INT is active HIGH.
BUSY: This Signal indicates that the 8087 NEU is executing a numeric instruction. It is con-
nected to the CPU"s TEST pin to provide synchronization. In the case of an unmasked excep-
tion BUSY remains active until the exception is cleared. BUSY is active HIGH.
READY: READY is the acknowledgement from the addressed memory device that it will com-
plete the data transfer. The RDY signal from memory is synchronized by the 8284A Clock
Generator to form READY for 8086 systems. For
80186/80188
systems, RDY is synchronized
by the 82188 Integrated Bus Centroller
to
form READY. This signal is active HIGH.
RESET: RESET causes the processor to immediately terminate its present activity.
The signal must be active HIGH for at least four clock cycles. RESET is internally synchronized.
CLOCK: The clock provides the basic timing for the processor and bus controller. It is asym-
metric with a 33% duty cycle to provide optimized internal timing.
POWER: Vee is the +5V power supply pin.
GROUND: GND are the ground pins.
NOTE: For the pin descriptions of the 8086, 8088, 80186 and 80188 CPUs, reference the respective data sheets (8086, 8088,
80186, 80188).
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