Sharp PC-4741 Service Manual page 16

<1J
10 MHz SLOW cycle (10, DMA, REFRESH cycle)
CPUCLK
SVLD
SYSCLK
ALE
-
P C--4741
SMRDSIORD
--------------------~----~------------~-----+------+-----_r--------------­
SMWR SIOWR-CPU CYCLE
SMWR SIOWR-DMA AND REFRESH CYCLES
STC
RDYV40
3-11. Printer interface
Fig, 3-12 shows a func1ional block diagram of the printer interface
circuit. This circuit consists of the print data register, printer status
port and printer control register.
The print data register, which is assigned at the 110 address 378H or
3BCH, stores data to be sent
to
the printer. The contents of this
register can be read
by
the CPU at the
va
address 37BH or 3BCH via
the buffer.
The printer status port reads status information sent from the printer.
This port is assigned at the 110 address 379H or 3BDH.
The printer control register stores control codes to be sent to the
printer. This register assigned at the 110 address 37AH or 3BEH. Bit 4
of this register determines whether the ACK signal from the printer
makes enable or disable as the CPU interrupt signal. When this bit is
HIGH, interruption is enabled.
The contents of this register can be read by the CPU at the
110
address 37AH or 3BEH.
Assignment of the printer interface 110 address to either 37XH or
3BXH is dependent on the state of PPSEL (parallel port select bit 4)
of the PC-4600 register CFR (Conffguration Register) which is as-
signed to the 1/0 address 7FH. If PPSEL is 0, the printer interface 110
address is assigned to 3BXH. If PPSEL Is 1. the address Is assigned
to 37XH.
It is possible to disable the standard printer adaptor by resetting PPS
(bit 1) of the PCR (Planar Control Register) 110 address 65H which is
normally set on.
Table 3-2 shows the printer 110 address definition.
Fig. 3-13 shows the printer timing chart.
-15-
READY SAMPLE#2
THIS SECTION REPEATED IF
EITHER READY SAM PLE .. O
L
READY SAMPLE#1
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SAO~
SA15
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"""'"
Inp~VOulpU!
buHer Dala latch Bufler
a
Selec!or
YOO
25-pln D-she!1
conector
DATO~DAT7
A ."",.,..
y ,
I<----1K
flI<c..;...--1<J--~';'"-I ;~LECT
-
C BUSY
Confrulla1ch OU1pU! buffar B~ffer
InpUL
buHer Deceder
_VG301A
PC .. HOO privale reglSLers (GaLe anay)
Fig. 3-12 Function block diagram