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-,
~--~------------------~~-------------------
------if1~l=
3·15.1~1.
Confrorregister-O
This
an
8~bit
write onl)ilegisfer .
.:
. '
,
-r'
iSit ",.
, .
" _
Si9fl'ific~lIice~
: position
Syinpol
:
Name
.
.""
.
07
MEN3
Motor enable-3
Control bit
to
control
the'
"'.
-~
-
lJ'lotqr in: the
NO. 3 ..
<lrive
,
. '
,
vnit.
':
,
06
MEN2
Motor enable-2
Control bif
io
""nttol the
motor in the
No.2 drive
.::.
:unit.:~:
-
,>
-
,
..
. OS.
.
,
MEN1
Motor
ena~l.e-1
C_ontrol bit
to
contr91- the
.~~9.~r~j~~.~~e:... N~.
,1 ___
~ri.,,~.
unit - :
:
04
MENO
Motor enable-O
Control bit to control the
motor in the No.
o
drive
-
.
,
unit
03
ENIO
EnablelNT
&
Used to set INTRO and
OMA request
CRGl2 into effect When
this bit is ai a low. INTRO
and ORQ2 stay inaCtive.
02
FRS!
Not FOC reset
User::! to reset trie internal
FOC. When this bit is 0,
the
foe
block is: reset.
01
OSS
Drive select B
Used to select FOC.
00
OSA
Drive select A
~~~;6~~:: O~A~elected
(0,0): No. 0 drive unit
(0,1): No.1 drive unit
(1, 0): No.2 drive unit
(1, 1): No.3 drive unit
Sut, if COS is low, those
bits are ,not in 'effect and
bits a'ra 'riot -in effect and
the .internal. FOC select sig-
nal becomes effective: All
bits'
will
be
'Cleared when
RESET is set high.
All bits will be cleared when RESET is set high.
Table 3-4
3-15-1-2. Control register-1
This an
a-bit
write only
regi$t~r.
Sit
Symbol
Name
position
03
63
Control-5
04
C4
Control-4
.
:02·.' SSM
Standby mode
PO
FOCTC POC letlllin,!! .
Sighificance
These - bits are open to
u&er •. Bit stat!3 appears on
CS and C4 ..
If C4 is connected
with
MIN,
for instance, the mini-
floppy
disk
can
be
changed to' the standard
floppy ·disk by ineans of
sqftware.
This bit
indicat~s
standby
mode~
' I .
-Standby mode. would not
oCc_ur Wht;ln
thi~
bit is at o.
Used to. con.trol tl\~:'FOC
counter
!
terminal count. When data
transfer is terminated in
the non-OMA mode, the
terminal count is sent to
the internal FOC black in
reference to this bit.
Table 3
,
-18-
Ailbitswijjbeclear~d whenRESETis set high.' FQrodaiabLis~
oI:Os,
D3, 01, are bit."able signallarOl!, D4;; OZ, ana OO;ifispCissioleto'
change bit independeNly.,
For
instanc$, V(riting,' 03H changes, only
FOCTC to
1
without changing thecantents of C6, C4; and SSM ..
3-15-2.
Interiflci~gthe
!"pC register with CPU
Interfacing the FOC register witli CPU:
The FOC has two registers which can be
aoCes~ed'
by the main
system processor.-- The one is main status, register and the
oth~r
is
data register. The main status register indicates the FDC,status-i-nfor-'
mation and can be _accessed 'at-'any·-'tiltfet.
The-
a-oit data:-regfster
stores data, command;, :pa-rameter~ -and - : FDO s~atus;- O~ta, byte' is
written in the data
rsgi~t~r-or
re.ad fr9mths_data
~egister
for
prQg,r~m
'11ing or to obtain the
re~u!~
after -command exec'ulion.
rJl~,
main'
status register is read only to
faciJi~~te d~~
transfer jjetweeo.UJ,e, F.OG
and the processor. The foll9,Wh'J9 shows the relation ,among the main
status register, data register, IOR,J9W .. and.CS.
Condition: A7=A6=A5=A4=A2=1,
A3~A1
=0,' AEN=O
CS
AO
1Ol'f
i5W _
Function.
Low
Low
LaW
.L,ow
Prohil;>ited .
.
.'.
Low
Low
Low
High
Main status register read
Low
Low
High
Low
prohibited
Low
High
Low
Lqw
Prohibited
Low
High
Low
. High
Data.register read
Low
High
High:
L,o,w ,
D~.ta
register write
Table 3-6
Each main status register
bit is
defined as in Table 3-7.
The main staJusregister bits, ROM and 010, indicate whether the
data register is ready or.Yihich direction data are on the data bus.
DIO _ _ - ' -_ _ _ _ - '
ROM
[oIOWJ-u
u
[.IOR] _ _ _ _ _ _ _ _ ,
r---,
Fig. 3-17 Main status register timing
A (0I0=low, ROM=high):
Data register is enabled to write by the processor.
S (ROM=low)
Data register is not ready.
C (OIO=high, ROM=high)
L
Data register is read by the. processor and a next data byte is already
on .
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