Sharp PC-4741 Service Manual page 50

4·16. BUSLOCK (bus lock) ... 3·state output
This signal js used to rAQIlAst the other master CPUs in the multi-
processor system nol to use the system bus while the instruction
following the BUSLOCK prefix is being executed or during interrupt
acknowledge cycles.
During bus lock (I.e. SUS LOCK is active). hold request and DMA
request are ignored, while refresh request is hold off.
This pin becomes high impedance during hold acknowledge.
4·17. POLL (poll) ... Input
The signal input to the POLL pin is checked by the POLL instruction.
If the signal is at the low level, the program execution proceeds to the
next instruction. If the 1'0[[
pin is at the high level, it is checked
every five clocks until the
'f'5()[[
input goes low. These functions are
used to synchronize the CPU program with the operations of external
devices.
4·18. BUFR/W (buffer read/write) ... 3·state output
This signal is output to determine the data transfer direction of an
external bidirectional data buffer. If it is high level, data are output
from the jlPD70208G to the external device. If the signal is Jow Jeval,
data are input from the external device to the !lPD70208G.
This pin becomes high impedance during hold acknowledge.
4·19. BUFEN (buffer enable) ... 3·state output
This Signal is active low signal and is used as an output enable signal
for the external bidirectional data buffer.
During T2 through T4 states of the read cycle and interrupt acknow-
ledge cycle, it becomes active (low level). This signal also becomes
active during T1 through T4 states of the write cycle.
However, the BUFEN pin will not become active when the internal
110
on the chip is accessed.
This pin becomes high impedance during hold acknowledge.
4·20. X2 and X1 (clock) ... Input
To use the internal clock generator, a crystal must be connected
across the X2 and Xi pins. The oscillation frequency of the crystal to
be connected should be 2 times the operating frequency.
If an external clock generator is to be used, the square wave of 2
times the operating frequency must be input to the Xi pin and the
inverted signal of the Xi to the X2 pin.
4·21. CLKOUT (clock out) ... Output
This pin outputs the square wave clock that has one half the frequen-
cy of crystal frequency or X1 input frequency.
1\·22.
BS2 to BSO (bus status) ... 3·state output
These pins output status signals that inform the external bus control-
ler of the current bus cycle.
These signals become active during T1 and 12 states and are en-
coded as indicated in the table below. By decoding these encoded
signals, the external bus controller can generate control signals by
which to access the memory or 1/0.
Only when CPU enters halt state. BS2 to BSO indicates the CPU
passive state one clock earlier than normal states.
BS2 BS1 BSO
Bus cycle
0 0 0 Interrupt acknowledge
0 0 1
1/0
read
0 1
0
1/0
write
0
1 1 Halt
1 0 0 Program prefetch
1 0
1 Memory read*
1
1 0 Memory write (including DMA cycle)
1
1 1 CPU passive state
" In addition to the CPU read cycle. the "memory read cycle" in'
cludes the DMA cycle. DMA verify. and refresh cycle.
These pins become high impedance during hold acknowledge.
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P C-4741
4·23. QS1 to QSO (queue status) ... Output
These signals inform an external device (floating-point operation chip)
of the CPU's internal instruction queue status.
The "queue status" means a status in which the execution unit (EXU)
in the CPU accesses an instruction queue. The contents output to the
OS1 and
aso
pins are valid only during one clock cycle immediately
after the EXU has accessed the instruction queue.
QS1 QSO Instruction queue status
0 0 No operation (no changing queue)
0
1 The first byte of
an
Instruction is fetched.
1
0 The queue is empty.
1 1 The
~econd
or latter byte of the instruction is fetched.
The status signals are provided so that the floating-point operation
chip can monitor the program execution status of the CPU and
per~
forms processing in synchronization with the CPU when the control is
given to the chip by the FPO (floating point operation) instruction.
4·24. TOUT2 (timer output) ... Output
This is the output pin of the internal timerlcounter unit (TCU). Of the
three counters of the TCU. the result of the TCT#2 is output to this
pin.
4·25. TCTL2 (timer control) ... Input
This is the control input pin of the internal timer/counter unit (TCU). Of
the three counters, the TCT#2 is controlled by this input.
4·26. TCLK (timer clock) ... Input
This is the clock input pin of the internal timer/counter unit. However,
the clock actually input to each counter is selected by software from
either the clock input to this pin or the operating clock of the
!lPD70208G on which frequency division has been performed.
4·27. INTP7 to INTP1 (interrupt request from
peripheral) ... Input
These seven pins input asynchronous interrupt requests to the
inter~
nal interrupt control unit (ICU). Either edge·triggering (at the rising
edge) or level·triggering (high level) of these input signals can be
selected. These interrupt request inputs can be also used to release
the standby mode of the CPU.
These pins have internal pull-up resistors.
4·28.INTAKISROY/TOUT1 (interrupt
acknowledge/serial ready/timer output) ... Output
This is a shared output pin for interrupt acknowledge Signal, serial
ready signal, and timer output (TCT#1). The interrupt acknowledge
signal INTAK becomes active (low level) during T2. T3. and TW
states of the interrupt acknowledge cycle of the CPU. The SRDY
signal is output from the internal serial control unit (SCU) and be-
comes active (lOW level) when the receiver is enabled to receive data.
The TO UTi signal is output from the internal timer/counter unit
(TCU). Of the three counters. a result of the TCTII1 is output to this
pin. The fUnctions of this pin is selected by contrOlling the OPCN
(on-chip peripheral connection) register in the IlPD7020BG by
software.
4-29. OMAAK3/TxO (OMA acknowledge/transmit
data) ... Output
This is a shared pin and outputs the acknowledge signal for channel 3
of the DMA unit and serial data from the serial control unit (SCU).
The OMAAK3 signal is active-low.
When this pin functions as the TxD pin, it becomes high level
(mark~
ing) if there is no transmit data. When transmit data is set, the start bit
(low level) is automatically output and then the set data is serially
output. A parity bit and a stop bit (high level) are appended 10
Ihe
end
of the each data. Whether to append the parity bit can be specified by
program.