Sharp PC-4741 Service Manual page 11

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--------~~:'!74~t~' --------------------------------------------~--------------------~------
3·6·3 Memory access timing
<D
Normal DRAM access
T2
CLKOUT
. 1 ' . ,
30-40 30-40
MA;
ROW Address
,:.Co!umn
Address
r~-
-',-,
'
'-, C \
--30--40:'
flg::H
DRArvr~q"esj!timi[lg (normal)
@ At DMA memory write
CLKOUT
- 0''-'
BS
10-55
10-55
10-20 30-50
Same as
<D
for the timing of OE, WE, RAS, and MA.
Fig. 3-7 DRAM access timing (DMA memory write)
®
ROM access
CLKQUT
A1B-A19
_I-Ij\...::::!:::.::~'+
_____
+-----
10-20
20-40 20-40
Fig. 3-8 ROM
access
timing
3·7_ 8087 interface
The interface log of 8087 is stored in LZ95H12. The signal connection
is shown in Fig. 3-9.
r;:::==1
aso
-aS1
V4O"
.
'.
8087
ADO-AD7
A8-A19
NMI~"++
~ ADO-AD7
A8-A19
R E A D y ' I - - - - - - - - - - -_ _
--.J
Fig. 3~9 8087 interface signal connection
3·8. READY control circuit
The signal READY(RDYll40):Jor WOis .contralled bY.LZ95Ht2.
LZ95H12 and LZ95J21 control EXTM, EXTIO, SLOCYC, and
~EADY
signals for the devices accessed. LZ95H12 determines 'tne bus cycle
according to these signals, to control
RDYV4d. The bkick diagram
is
shown in Fig. 3-10. ; ... c: .:
:1 •
AOO-AOZ
SOO-S07
:
SAO-SA19
vila
Fig.
~-1
0 Overall ready control signals
3·9. DMA control
!293J21
Although the V40 haS faurDMA channels, two i:hannels are used.
DRQ2 and DACK2 are used for controlling the floppy.
DRQ2
"-
DACK2
V40
DATA BUS
TCS566F
(~PD70208G)
H
(FDC)
Memol}'
Fig. 3-11 Overall DMA control
~ignals
.
,
When the V40 starts to DMA after setting 'the TC8566F register, the
TC8566F sets DRQ2 high. After the V40 receives this signal, DACK2
is set low to perform DMA transfer between the TC8566F and the
memory.
DRQ3 and DACK3 are used for controlling the hard disk. DRQ3 is
supplied from the LSI in the hard disk controller. When DRQ3 be-
comes high, V40 makes DACK3 low to perform DMA transfer be-
tween with the controller.
,
3·10. Bus cycle generator (including LZ95H12)
3·10·1. General
The LZ95H12 bus cycle generator produceslhe SYSCLK," ALE," STC,
SMRD, SMWR, SIORD and SIOWRsignals: 11 inte.preisflie READY
signal and drives
thf;) RDYV40~s_ignal
to'_controI
th'~ number"c,f
wait
states. The LZ95H12
det~rmines
the'speEtd'of
the devices involved in
the transfer. Deviees, are group-eo intoJhree speed categories:
1. fast AD bus devices;
2. fast SD bus devices; and
3. slow SO bus devices.
i=ast.AD devices are the V40, the SOS7,_the LZ9.5H12, the system
ROM, the system DRAM. Fast SO bus devices are those devices
Wniphare qqQtrbli!fdi;fy the LZ93J21!ar which the
SL0CYC
signal is
nat asserted. This signai is sampled altha start of first T-cycle fallow-
ing ,the assertion· 01 th&SMRD, SMWR, $IORD or SIOWR. At
7.16MHz, this occurs at the start of T:3. Ai 10 MHz this occurs at the
S!~rt
of the'first
TW~_'~IJ othe(ce~ices ~re
slow SO bus devices.
Th~rl?
are
ti1r~e SPE;!~c:f~,-of 11.~"n-r~fr~sh~cyqiE;!s: la~t,
medium
~lI:u;f
slow.
Fast speed cycle execute with no wait states, .9xcE!pt"for ;IQ,NMI
trapping cycles;-whicfi"take 'nine T-cycles. 'Medium speed cycles may
-- aiso"insert wait states in resp·onse to a.'-reset READY signal. A special
extended medium speed cycle that drives SYSCLK fram CPUCLK is
also implemented. At 7.16 MHz, the minimum medium speed cycle
takes 5 T-cycles. At 10 MHz, the minimum medium speed cycle takes
6 T-cycles. Medium and slow speed cycles have the same timing until
SLOCYC is sampled.
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