Sharp PC-4741 Service Manual page 51

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"E--G4Wo~
The PPD702QBG's'
irjtem~1
JWC;N,
(Q~~phip' peiipher~1
oonhegijorj)
register P?ntrqls
thef~ncti~n
Qf this pin (ieier to 12,1, Systeryl 1/0
Area), . . .
4-30. DMARQS/RxJ)
(DAMr~q~~st/~~C~iV~dlltll):
....
Input
This is a shared pin that iliputs the r"quesi slgnai iotchannel 3 of tile
DMA unit
iina
i5~ serial data of the SCU;' .-." '... .
The DMARQ3 signal is active-high, ' ' . . '
When this pin functionS
as
the RxD pin, a high-level (!11arking),signal
is inpl,lt t9 it when'n-o data is transmitted. The .'1xD.'-run)tarts receiViQg
da!~
at the falling edge of the start
])11:---- . . .
Pin
DMAAK:j/TxD' , I qMARQ3/RxD -
'I~TAKtSFlDY/1"9lJT!
, , . elecilon " ,
I,
, .. DMAAK3
DMARQ3
,INTAK.
,Z " '
"DMAAKL
".,DMARQ3.
,
,. TOUT!
3 TxD RxD
ifiJ1'AK
4
,IxD
RxD
...
SRDY
..
The
three pins des"ribed in Sections'
~2B
'through <!'aOoan be
specified in the fallowing four ways by controlling register OPCN (on-
chip peripheral connection) o(the I'PD7020BG by software,
4:'31. DMAAK2to DMAAKO(DMAllcknowledge) ...
Output
These pins output the DMA acknowledge signals, from channels 2
through 1 of the DMA unit.
These'signals are active-low. '
4-32-. DMARQ2to DMARQO(DMA request) ... Input
These pins input the DMA recjuesi'slgnals to charinels 2 through
a
of
the DMA un~.
These signals are active-high:
4-33. ENDITC (end/terminlll count) ... Input/output
This',activ9'-lbw pin controls
termiriation
cif data transfer by bMA:whe'n
the 'data transier is performed by the DMA unit. When a 10w-lEiI,el
pulse
(END)
is input to this pin during the DMAtransfer, the DMA unit
will terminate the ongoing
DMA s,eryicing.
Also, when' the number of
DMA ransters specified for each channel is complete, this pin outputs
a law-level pulse
el'C),
Because this pin is an
o'pen-draJn,
'a'pull~up
resistor
must be external-
ly
con'r'iscted. .
4-34.
VDD
(power supply.)
This is 'a'
positiv~
power'supply pin;
4-35.GND (ground)
Th,is is a ground pin (OV),
4-36. IC
(int~rnIlIlY
CO,I1"E!cted)
Dontconnect any signai'With:this'pin and' must be left open;
-50-
5. Functional Blocks·
5-1. CPU (cerifral processing onit)
Tne CPU eonsists oft ... o independerit processing units: BCll (bus
co~t!'01 unit) and EXU (execution un~), Each of these lwdUilits per-
forrns the'followlngfunction ... , .. . " . . . . . . . .
BCU ................. Prefetches'instructions ,using instruction-queues;
(the
"instruction queue'is 4-bYtefor the I'PD7020BG.
EXU" ................ Processes data
(ex~cu~~~,microp~o_grams'-.
_.
•
LC
PC
AW
BW
cw
ow
IK,
IY
BP
SP
PSW •
NMI
INT
~=rr'7 ~T:"=.,r;-,
-;;:(irom'cG}
, CLOCK
i(fremCG)
..
-.---------.~p..!:!..
EFFECTIVE ADDRESS
GENERATOR
EXU
oo~
OOW
~ ~
.
INST.RUC~JON
Miqro, data
C
C!l
ROM
bus
ow
~~
Queue data
,,",,",=:;;"'1
. bus
(~-8J~-====:...,...,
INSRTRUCTJON DECODER
Sub data bus (16) 'Main data'bus (16)
Fig, 5-11'PD7020BG CPU black diagram
.
.
5-2. BIU (bus interfllce' unit)
The BIU controis the pins'
constituti~g
the data bUS,
a~dress ~iJsi
and
control bus.
Th~se
buses
ar~ U!~ed:
by tJ:!ree Junct.jonal
~I~cks:
the
CPU, DMAU(DMA control unit), and REFU
(refr~sh
control unit), The
BIU synchronizes. the RES~T.' and READY ·inpu!s using lheclock
signal generated by the clock
genera~or.
The
synchr0r:!iz,~~ re~et ~i.g­
nal is active,high thetis used in the j.lPD7020BG as wei! as ,supplied
to an external device vi~ the RESOUT pin, The syn,chronized READY
signal is supplied!o the internal CPU,
DMAU,~nd
REFU,
CWCK--~------~-------,
READY~---'--'-i
1lI---,-~RESOtJT
To internal
drcuJt
To lrjternal
circuit
Fig, 5-2'
Synphronizatio~
of
REsEr
and READY