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P C-4741
4) Signal description
PinNa.
Signal name
In/Out
Description
1
C6
Out
Control register C6 output
2
iOR
In
Signal used to transfer data onto the data bus from the FDC.
4
lOW
In
Control signal to transfer data from the data bus to FDC.
5
AO
In
6
A1
In
7
A2
In
8
A3
In
Address signal
9
A4
In
10
A5
In
11
A6
In
12
A7
In
13
CS
In
FDC chip select
14
AEN
In
Address enable from the CPU
15
DO
In/Out
16
D1
In/Out
17
D2
InfOut
18
D3
In/Out
Bidirectional 8·bit data bus
19
D4
In/Oul
20
D5
In/Oul
21
D6
In/Oul
22
D7
In/Out
23
DR02
Out
DMA request. Output to delay DRO. The signal is at a low level when Ihe conlrol register ENID bit is O.
24
INTRO
Out
Interrupt request issued by Ihe FDC. The signal is al a low level when Ihe control regisler ENID bit is
O. This signal stays low.
25
INT
Out
Interrupt request issued from the FOG.
26
DRO
Out
DMArequesl
27
[VSS)
G
FDC digital ground
28
AG
G
VCO
analog ground
32
DACJ<2
In
DMA cycle becomes valid with a low state of this as input at DMA transfer.
33
DMATC
In
Indicates end of DMA during DMA transfer.
34
CONT
In
VCO
control voltage input
35
TEST
In
Test input with a pullup resistance. Normally, not to be connected or fixed high.
36
VCO
In/Oul
Test input in the test mode, but normally output. To be connected with the low gain side filter.
37
LPF2
Out
Output connected
10
LPF of Ihe PLL circuit. Selected after leading frequency. To be connected with
the low gain side filter.
38
LPF1
Out
Output connected to LPF of the PLL circuit. Selected after leading frequency. To be connected with
the high gain side filter.
39
CW
Out
Test input. Not to be connected.
40
DW
In
Data window input signal required when using external VFO circuit. Normally, low or high fixed.
41
FLT1
Out
Test input used to indicate filter switching. Not to be connected.
42
DOS
Out
Test input. Not to be connected.
43
LOCK
In
Test input with a pullup resistance. Normally, not to be connected or fixed high.
!Wi
Data read signal from the floppy disk drive.
44
(RDT)
In
When the external
VFO
circuit is used, it is a data read signal (RDT) input from the external
VFO
circuit.
45
XOUT
Out
Crystal oscillator inverter amp output pin.
46
XIN
In
Crystal oscillator inverter amp input pin which is used for the 16MHz external clock.
47
I.il'OEN
In
Internal VFO select signal. Internal
VFO
is selected with a low state of signal and the external
VFO
is
chosen with a high state of signal.
Used to select the standard floppy disk and mini-floppy disk.
48
MIN
In
Low: Standard floppy disk
High: Mini-floppy disk
49
MFM
Out
High: MFM mode
Low: FM mode
53
IT
In
This pin incorporates a pullup resistance and is used to reset the internal clock generator and VFO
flip-flop with a low state of signal. Normally, not to be connected or fixed high.
54
[VSS)
G
FDC digital ground
55
SYNC
Out
Indicates that the FOC is in reading action.
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