Sharp PC-4741 Service Manual page 20

Bit
I
Position Symbol Name Significance
D7
ROM
Request for Indicates that data are sent
master
to the processor from the
data register, or it is ready
to receive data from the
processor.
D6
DIO Data inpuVoutput
Indicates
data
transfer
direction when transferring
data
between
the data
register and the process
or. A high on this line indi-
cates that data are trans-
ferred
from
the data
register to the processor.
A Iowan this line indicates
that data are transferred
from the processor to the
data register.
DS NDM Non-DMA mode
Indicates that the FOC is in
the non-DMA mode. This
bit
can
be active only in the
execution phase of the
non-DMA mode. A Iowan
this line indicates that the
execution phase has been
completed.
D4 CB FDC busy
This bit is set when a read-
wirte related command is
in execution or during ex-
ecution of command phase
or result phase.
D3 D3B FDD3 busy Indicates that the NO. 3
drive is in the seek mode.
D2 D2B
FDD2 busy Indicates that the NO. 2
drive is in the seek mode.
D1 D1B FDD1 busy
Indicates that the NO. 1
drive is in the seek mode.
DO DOB
FDDO busy Indicates that the NO. 0
drive is in the seek mode.
Table 3
R
7. Main status register
The FOC may execute 15 different commands. Execution takes place
with a multiple byte transfer by the processor, and results after com
R
mand execution is indicates after multiple byte transfer to the proces
R
sor. For multiple number of bytes are transferred between the FOG
and the processor, it may be assumed to constitute the following
blocks.
Command phase:
The FOC receives from the processor information required for the
given operation.
Execution phase:
The FOG executes the given command.
Result phase:
After completion of the operation, the result status information are
sent to the processor.
During execution of command phase and result phase, the processor
needs to read the main status register before the byte information is
written in the data register or read byte information from the data
register. In order to write command and parameter bytes in the FOC,
the main status register bit 07 must be high and bit 05 low. For
majority of commands requires a multiple bytes, the main status
register must be read before transferring bytes to the FOG. Also, the
main status register bits 07 and 05 must be high before reading
bytes from the data register during execution of the result phase. For
the command phase and result phase, the main status register must
be read before transferring bytes to the FOC, but may not be required
necessarily for the execution phase. When the FOe is in the non-
OMA mode, receive of data bytes (when the FOe is reading data
from the FDD),INT (INT=1) is caused.lfTOl'i (lOR=O) is issued, it not
-19-
-
P C-4741
only send data on the data bus, tNT may also be reset. However, if
the processor may not be fast enough
to
handle the interrupt (within
13J.lS in the MFM
m6C9}~e
main status register
IS
Interrogated. I
he
bit 07 (RQM) function as INT. In the same manner, tNT may be reset
with
iOW
while write command is in execution.
INT is not issued while the execution phase is being executed when
the FDC is in the DMA mode. The FDC issues DRO (DMA request)
when data bytes are ready, to which the controller set
Ii7iC
low (DMA
acknowledge) and
TOR'
low to respond to it. ORQ is reset when OMA
acknowledge is set low for a read related command. For a write
related command, TOW functions the same as
~.
An
interrupt is
request upon completion of the execution phase (Te received) which
indicates the start of the result phase. After reading the first data byte
in the result phase, INT is forced to reset. In the result phase, all data
bytes shown in the command list must be read. For instance, in the
result phase of read data command, there are seven data bytes. In
order to finish the read data command, these all seven data bytes
must be read. Otherwise, the FOC may not receive a new command.
For other commands, all data bytes must have been read in the result
phase. The FOC has five status registers. The above mentioned main
status register may be read at any time by the procesor. Four result
status registers (STO, 8T1, ST2, ST3) can be used only in the result
phase and can be read at the termination of command. Size of the
result status register depends on the command executed. Sequence
of data bytes sent to the FDG in the command phase and data bytes
read from the FOC in the result phase is as shown in the command
list. In other words, a command code must be first sent,
to
be fol-
lowed by other bytes in the given order. So, nothing could be short for
the command phase and the result phase. When the last data byte of
the command phase is sent to the FDG, the execution phase takes
place automatically. Similarly, after reading the last data byte in the
result phase, the command automatically terminates and the FOC
becomes ready to accept a next command.
3-16. Keyboard i nleriace
IRQl
KDATA
~
DATA BUS KCLK
V40
LZ95H12 SCM
KSENO~
10
Fig. 3-18 Overall key signals
The SCM issues strobe through KSTRO-1 0 at every 6ms to scan the
level on KSENO-7 to sense key depression. The code is sent to the
LZ9SH12 on KDATA with a clock on KCLK. The following shows its
timing.
KDATA
:=:::=::x::==x=
KCLK~
After receiving the code in the shift register, the LZ95H12 turns IRQ1
high with which the V40 read the data from the LZ9SH12.
(2) Keyboard LEDs (CAPS LOCK, NUM LOCK, SCRL LOCK)
, -
CPUHS
DATA BUS
ICPO-3
D~ver
V40
Llg5H12
SCM
>=
SCMHS
K~~22
LE01~3
L - -
Fig. 3-19 Keyboard LEDs
LED is activated after the SCM receives the command sent from the
V40 via the LZ9SH12. Communication between the LZ9SH12 and the
SCM is carried out by handshaking. The data are sent on four bidirec-
tional bus ICPO-3. The signal CPUHS is used from the LZ9SH12 for
handshake control and SCMHS from the SCM. The figure below
shows an example of data transfer.
CPUHS~
ICPO-3 to S M t SCM
SCMHS
1
SCM read SCM read