Chapter 9. Appendices - Sharp PC-4741 Service Manual

2. IlPD7020BG Pin Configurations
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P C-4741
CHAPTER 9. APPENDICES
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Clastic Slat Rackage (Top View.)
9-1. I-lPD70208G Main CPU (V-40)
1. Features
1-1. High-performance B-bit CPU
o 1 M·byte memory space and 64K·byte 1/0 space
o
Abundant memory addressing modes
o Fourteen i6-bit register sets
o Instruction set with 101 types of powerful instructions
o Bitfield manipulation instructions
o Packed BDC arithmetic operation instructions
o Memory-memory high-speed block transfer instructions
o High-speed multiplication and division instructions by exclusive
hardware
o High-speed effective address calculation by exclusive hardware
o
A
wealth of interrupt process functions
o llPDBOBOAF emulation mode
o Standby mode
1-2. Internal clock generator
1-3. Programmable wait function
1-4. Dynamic RAM refresh function
1-5. Timer/counter unit
o Three 16~bit counters
o Six programmable count modes
o
binary/BCD count
o Multiple-latch commands
1-6. Serial control unit
o Asynchronous serial communication
o Clock rate: Baud rate x16, x64
o Baud rate: DC to 48.4k bits/sec.
o
Character lenglh:
7/B
bits
o Transfer stop bit:
1/2
bits
1-10.IEEE-796 bus compatible interface
1-11. CMOS
1-12. Low power consumption
1-13. Single power supply
1-14. 10-MHz clock
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~PD7020BG
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NOTE: For "PD7020BG, pins 3 10 10 are ou1pul only.
3. IlPD7020BG Block Diagram
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X~X
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TOUT2
TOUT1
TCTL2
TOlK
lNTP7
INTP6
INTPS
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INTP4
[NTP3
s:
lNTP2
INTP1
lNTAK
NMI
X2=f8l
Xl
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mao
POLL
BUSLOCK
BUFEN
BUFR/W
HIGH
ASlB
IoWA
lORD
MWA
MAO
READY
RESOUT
RESET
HLOAK
HLDAQ