Sharp PC-4741 Service Manual page 55

________
~.4E~G~il----------------------------------------------------------------
Symbol
ADI5-ADO
A19/S6." _
A18/S5,
A17/S4,
A16/S3
BHE/S7
S2,S1,SO
imlGTO
Type
1/0
-
,:~
-'
..
Table 1.
8q87Pin.D~scription
Name and' Function
ADDRESS DATA: These linei~H:oristitute the time multiplexed memory address (Tl) and data
(Ta, T3, Tw, T4) bus. AO is analogous to the BHE for the lower byte of the data bus, pins 07 -
DO:. It is LO\iV duringTlwhen a byte i"to.b,,)ransferred?q,th.elqwerPor:tionoUhe,bu,s)",
memory operations. Eight,bit oriented devices tied to the'lciwerhillf bftheMs wbuldnorinally-
useAO to condlti()n chip select functions. These Jines are active HIGH, they areinpuVoutput,
lines for S08Hriverr bus cycles and are. inputs Which
ina
S'OS7'milnltons'when theicpLl is:i,;
control of. the bus. A
15~
AS do not require an address lat,;h;h an80SS/SQ87. or S018S/89s7,the
8087'will'sQIlplYllWaCidress for the Tl - 14 period;-'~' ""., .'.,-,,- -. -,
0 0 . . . . . ' ' , ; ;
_.
~J!9..
c.
ADDfiESl? MI'MQBY:.DOting Tl these are the four most significant address lin'es formemary
operations. During memory
operatio~,r,'
statusinform!!tiO]1 isayail"pll! aD'lhese linel1dUrirfg;Ja;.
T3, Tw, and T4. For 8087-controlled bus cyci!ls,~6. ;;4,!!~.d.~~?reres~ryed.!!nd:currentiY;il~e
(HIGH), while S5 is always LOW. These lines are inputs which the SOS7 monitorswhent(1s.CPU
is in control of the bus. .." .. ".
J .•
~
-
~
• . ; . . . , .
1/0
BUS HIGH ENABLE: During Tl the bus:llighenablesigneo(BHE)'should
be
used
10:
enable·
data onto the most significant half of the data bus, pins 015 - 08. Eight-bit-oriented devicesii"d
to the upper half of the bus would normally use BHE to condition chip select functions. BHE is
LOW during Tl for read and write cycles when a byte is to be transferred on the high portion of
the bus. The;;! status information is available during,
Ta,
13, Tvy"and; T4 .. Thesign!!1 is.<\c::tive
LOW ..
S7
is ~n input whichthea087 monitors during the CpLi~coiiircillEidb4sciyqles ...... "
,"
1/0
1/0
, STATUS: For 8087-driYen, thes.estatu" IinEl.s are!!BcQqed as follows:
J"
S2 . S150, . .
o (LOW) X X Unused
1 (HIGH) 0 0 Unused
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
Status is driven active during T4, r",mains v!!lidduring Tl and T2, and is returned to the passive
state (I, I, 1) during'T3 or during Tw when READY is HIGH. This status is used by the 8288 Bus
Controller (or the 82188 .Integrated Bus Controllerwithan 80186/80188 CPU) to generate all
memory access control signals. Any change in S2, SI, or SO during T4 is used to .indicate the
beginning of a bus cycle, and the return to the passive state in T3 or Tw is used tej'jndicate the
end of a bus cycle. Thes ... signals are monitored by th .. 80S7 when the
yPW
is in control of the
bus. '. . • . . _
' " . C .
REQUEST/GRANT, This requesVgrant pin is used by the 8087 to gain control of the local bus
from the CPU for opefimd transfers or on behalf of another bus master. It must be' connected to
one of the mo
proc;:e~sor
requesVgrant pins. The requE1sVgrailt sequence on this pin is as
follows:
1. A pulse one clock wide is passed to the. CPU to indicate a local bus request by either the
8087 or the master connected to the 8087ROiGTI pin.
2. The 8087 waits for the grant pulse
ana
when it is received will either initiate bus transfer
activity in the clock cycle following the grant or pass the grant out on the RQ/GTI pin in this
clock if the initial request was for another bus master. ;
3. The 8087 will generate a release pulse to the CPU one clock cycle after the completion of the
last 8087 bus cycle or on receipt of the release pulse from the bus master on RQ/GTI ..
For 80186/80188 systems the same sequence applies except RQ/GT signals are converted to
appropriate HOLD, HLDA signals by the 82188 Integrated Bus Controller. This is to conform with
80186/80188's HOLD, HLDA bus exchange protocoL Hefer to the 82188 data sheet for further
information.
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