Sharp PC-4741 Service Manual page 17

--------~Rec4n~f--------------------------------------------------------------
BUSY·_~='1_4··~..
i ........... __ _
.~--ACK ~
.
-~--
;
..
, . "
.
DATA
--_~\-L--=3;S~
___ -
STROBE
---+-,)
Appro)(.511S
Approx.7lls
Fig. 3-13 TIming chart
___
~ ~
__ ,_,T'
_ " ~
-ReaClr-
~--
-"
~-"
110
Address
Write
Bit
Description
sSi-!
"PJW
i 1 PPS:
_ 0
-
.
1,.. Enables-tho"standard- printer
adaptor (normally set 1).
7FH
-FfNl
o
4
0- -
PPSEL
O (Paraller1'6ri
Select)
...
-O;Printeradaptor-I/O address
is assigned to 36XH.
..
-
1; Printer adaptor 1/0 address
is assigned to 37XH.
-----
PPSEL RNI 0 Print data 0 (LSB)
3BCH
0
1
Print data 1 .
2 Print data 2
3 Print daia3
4 Print data 4
378H 1 5 Print data 5
6
Print data 6
7 Print data 7 (MSB)
-----
PPSEL R 0 Not used (0 read)
3BDH 0 1 Not used (0 read)
2 o
or
1 read
3
Ei'iFiOR
read
379H 1 4
Sl;bECT read
5 PE.read
6
AeRread
7
.liUSYread
~
PPSEL
RIW
0
STROBE written
3BEH 0
1
AUTOFD written
2 mwritlen
3 SEL wriften
37AH 1 4 IRdENA, 1; Enables interrupt
request.
5 Not used (0 read)
6
°
Not used (0 read)
7 Not used (0 read)
Table 3·2 1/0 address definition
3-12. Serial interface
As
a standard, the PC-4700 has a serial interface wt1ich is
assigned
at the
110
address 3F8H through 3FFH or 2F8H through 2FFH.
Assignment of the serial interface 1/0 address to 3FXH or 2FXH is
determined by the
scM
(LU57832) output signal COMl/2. When
COMlt2 is at a low, the serial interface 1/0 addres,: is assigned to
3FXH. If high, the address is assigned to 2FXH.
-16-
IRQSA
-~--7--'4
SDo--SD7
SAO-SA2
CSCOMB.=~
SAEN
SJOAD
SIOy.'R
i "
RESET
--
...
-----
....
=
---_!_- •• _------ ••••
DS14CB8
f!~:?~?~.
DO~D7 INTRPT
TXO:
aUT2
AO-A2
SOUT
OTR':
DTR
CS1
R'FS
RIS:
CS2
01STR
SIN
!;lOBTA
DCD
CTS
'~~~==~l-::
f--.;-oRXD:
' & -
oeD:
MR DSR
XTAL1
RI
XTA12 UART
82C50AV
L.."-'-/
jC~+:
:c,j'
-·'GTS
i
_~~~<:~~-.DSR:
DS14C89A
.:1-",",t""'--+-"
RI
'-----
....
'
9-pin connector
Fig. 3-14 Serial interface circuit
The serial interface circuit consists of transmitter 0814C88, receivers
DS14C89A and the UART (INS82C50A). The convert TTL compatible
signals sent from the UART to -12V
to
+ 12V signals conforming to
the EIA standard, and output them via the RS·232 connector. The
convert the ErA level reception Signal to the TTL level and send it to
the UART. The functional configuration of the UART is programmed
by
software via the data bus.
The UART
p~rforms.
a
serial-to~parallel
conversion
of
dat~d:haracters
receI~ed fr0
rTl ' a;
peripherar
device or a,
MotiEM. and ~ ,performs
a
pa'ralfel-t6-seriaI conversidn
of
data characters
reCeived
from the
CPU. The CPU can read the complete St~tus of the UART any time
during the functional
operation~'
Status,
information includes
the type
and condition oUhe, transfer. operations performed by,th.8
UART,'
and
provides error conditions (pari't)', overrun; framing, or break interrupt).
The UART includes a programmable baud rate generator. Also the
UARl'
ras
a complete .modem control·.capability and a processqr-in-
terrupt system that: minimizes. the· computing· time for handling the
co,rpmu~ic~tions lin~.
When .the CPU assigns one of the: address 3FSH thrQugh .3FFH or
2F8H throu 2FFH as an 1/0.address,the,oHIGH
leve~CSC0MB
signal
senUram the.·VG301
A
(Gate Array) .is. emitted to the. UART. The
UART therr selects the internal register to.. b. ZORC .con.nected to the
data bus according. to.. the state of the DLAB (Oiviso( Latch Aqcess
Sit). The DLABis bit 7 of the line control register .. Table lists the'state
of registers indicates at .each 1/0 address, and the table lists the bH
assignment of each reglstei'.
.
I/O
. A2 Al AD .
mmm
lmlWI!
·O.LAB
Add"rE!~s,
.
,
.
: 3F.8H.or2F8H.
L
L L
L
H
X
3F8H or 2F8H
L L L
H L
X
3F8H or 2F8H L ~ L
.*
* 1 .
3~9H
or2f9H
L L H
* !I'.
1.
3F9H or 2F9H
L L H
* *
D
3FAH or2FAH
L H L. ,
*
*- X.
3FBH or2FBH L H H
* .*
X
3FCH or2FGH H L L
*
*
X
3FOH or2FOH
H
L H
* *
X
3FEH or2FEH H H L * *
X
*;
SJWiiJ
becomes LOW at read operation
§ClWR becomes LOW at write operation
X; Not applicable.
..
Receive buffer register
Transmltholding re"gismt-:",
Divisor latch LSB;
Divisor
ia~~h L~B
Interrupt
en~ble
register
Interruptidentificatioll reg!ster
Line control' register "
Modem control
regi~r
Line status register
Modem status register