Sharp PC-4741 Service Manual page 18

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110
Address
Bit
Description
-eF9H~H
-9-
~, Blable-<iata~
Interrupt
1
H: Enable TX holding register empty
enable
interrupt
register
2
H: Enable receive line status interrupt
3
H: Enable modem status interrupt
4-7
Always LOW
3FAH or 2FAH
0
H: No interrupt pending
Interrupt
1
Interrupt identification bit
0
identification
2
Interrupt identification bit 1
register
3-7
Always LOW
3FBH or 2FBH
0
Word length select bit
0
Line
1
Word length select bit 1
control
2
Number of stop bit
register
3
Parity enable
4
Even parity select
5
Stuck parity
6
Set break
7
Divisor latch access bit (DLAB)
3FCHor2FCH
0
Data terminal ready (DTR)
Modem
1
Request to send (RTS)
control
2
Out 1
register
3
Out2
4
Loopback
5-7
Always LOW
3FDH or2FDH
0
Data ready (DR)
Line
1
Overrun error (OR)
status
2
Parity error (PE)
register
3
Framing error (FE)
4
Break interrupt (BI)
5
Transmit holding register empty (THRE)
6
TX Shift empty (TSRE)
7
A'rways LOW
3FEH or 2FEH
0
Delta clear to send (DCTS)
Modem
1
Delta data set ready (DDSR)
status
2
Trailing edge ring indicator (TERI)
register
3
Delta dala carrier detect (DDCD)
4
Clear 10 send (CTS)
5
Data set ready (DSR)
6
Ring indicator (RI)
7
Delta carrier detect (DCD)
3-13. Speaker interface
A small, permanent magnet speaker is used in the sound system.
The speaker can be driven from one or two of sources.
It also can be driven by Ihe SCM, CE-462M (modem).
An LZ95H12 output bit
• A timer clock channel. output programmable within the function of
the V40 timer. The timer gate can also be controlled
by
the
LZ95H12 PPI output port.
vee
8111
of the port
I061H
Dlp-SW
V40
tout2
Drlver
Pin41
MSPKR
(From MODEM)
SSPKA
-----0--0
Fig.
3~15
Speaker controll circuit
3-14. RTC/CMOS RAM circuit
CPUHS
Data bus
LZ95H12
IPCQ-3
V4Q
(Gate array)
,
SCM
-
SCMHS
LU57B44P
32.768KHZJ:--1
m-i
Fig. 3-16 Overall RTC signals
-17-
-
P C-4741
The SCM has a 32.768KHz crystal oscillator for tho limor clock be-
sides the program executing oscillator, and divided to cause an inter-
rupt to the SCM Itself at the given Interval. 11mer clock
IS
counted
ih
this interrupt routine and stored in the internal RAM (C-MOS RAM).
This value can be read by the V40 via the LZ95H12 by means of
handshaking.
For setup data are contained in SCM internal RTe and others, they
can be read and written from V40 via LZ95H12 as handshaked with
SCM, similar as RTC.
3-15. FDD interface circuit
Tho FDD intorface circuit supports two floppy disk units at a maxi-
mum. Fig. 3-16 shows the block diagram. A TC8566F floppy disk
controller is used to interface the floppy disk units with the CPU.
FDC
NOTE: The 74HC157 is used to select between the built-in 3.5 inch
FDD and optional 5.25 inch FDD for drive A in the set-up
menu.
Fig. 3-16 FDD interface block diagram
3-15-1. TC8566F floppy disk controller
The TC8566F floppy disk controller contains a VFO and peripheral
logic circuit on a single chip.
Two control registers, main status register, and data register are on
the chip. Table 3-3 shows the relation between address line and
registers.
AEN ~
A7
A6
A5
A4
A3
A2
A1
AO
Function
H
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
No selection
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
H
X
X
X
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
L
L
L
H
Prohibit
H
L
L
H
H
H
H
L
L
H
L
Conlrol regisler-O
L
L
H
H
H
H
L
L
H
H
Control register-1
L
L
H
H
H
H
L
H
L
L Main status register
L
L
H
H
H
H
L
H
L
H Data
register
L
L
H
H
H
H
L
H
H
L
No selection
L
L
H
H
H
H
L
H
H
H
Table 3-3

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