Sharp PC-4741 Service Manual page 49

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4. Pin Function
4-1. AD7 to ADO
(add~~Ss/data bus).~.3-sfaie
input/output
These pins constitute a maltiplexei:J address/data bus that outputs the
lower 8 bits of 20-bit· address iriforinidion· and, Inputs/outputs 8-bit
data on a time-division. basis. These pins function as the address bus
during T1 state of the bus' cycle, and as the data bus during T2, T3,
TW, and T 4 states.' , : . "
These pins.
beicome
hiQh impedance during hold acknowledge.
4"2. A15 to M(address bus) ... 3-stateoutput
These pins outp~t th~Jnlddle 8 bits of 20-bit address. information.
These pins beCOme high impedance during hold acknoWledge_
,---
_.
- ,,.
. '
4-3. A 19/P$3' to
A
16/PSO (address bus/processor
status) ... 3"state output '.' . .
These are tin1e-muitipiexed output pins that outpot addresses and
processor status sign~s.
These pins function. as an address bus during T1. state' of the bus
cycle, They output prdcessor status signals during.T2, T3, TW, and
T4 states_ . ' . .
When functioning as an address bus. these pins output the higher 4
bits of address information. All tliese pins output 0 during 110 access.
The processor status siglial is output during .both the memory and I/O
accesses. The PBS pin outputs 0 in native mode and when the cycle
is neither DMA hor refresh; otherwise, it outputs 1. The PS2 pin
outputs the content of the interrupt enable flag (IE).
The PS1 and PSO pins indicate which segment is used by the current
bus cycle_ .
Processor Status
.-".
'
,"-
~
A17/PS1 A16/PSO
Segmenf
a a
Data segment 1 (DS1)
0
1
Stack segment (SS)
1
a
Program segment (PS)
1 1
Data segment a (DSO)
These pins become higl; impedance during hold acknowledge.
4-4. REFRQ (refresh request) ... Output
This is an output pin that outputs an active-low signal during T2, T3
and TW states Of the refresh cycle.
4-5. HLDRQ (hord request) ... Input
This pin inputs a high-level signal .when an ,external device requests
that the address bus;' address/diita bus, and, control bus be released.
The priority of thissignaUs
ail
101l0ws: REFU (highest priority) >
DMAU > HLDRQ > CPU> REFU (lowest priority).
4-6. HLDAK'(hold acknowledge) .•. Output
This signal indicates that the ~PD70208170216 has acknowledged
the hold raquest sigoal (HLDRQ) and set the buses to the high-im-
pedance state. When this signal is at the high level, theiefore, the
address bus, address/data bus, and control bus of 3-state output
system become high-impedance state, ,- "
If a refresh request or DMA requesi withhigher.priortty than the
HLDAK signal occurs during hold' acknowledge, HLDAK becomes
inactive. Then the
~PD70208G
requests that the bus control be
returned to it provided that the HLDRQ signal becomes inactive at the
same time.
4-7. RESET (reset) ... Input
This is an active-low reset input pin and takes the precedence over all
the other operations. The reset operation affects not only the CPU but
also the on-chip peripherals. After the reset input is released, the
CPU staris executing the program from address FFFFOH. The
l'iElffiT
input is also used to release the standby mode of the CPU.
-48-
4-8. RESOUT (resefoutput);.: 0!-ltput .•
~~..
,._
This pin synchronizes the asynchronous signal input to the RESET
pin
w~h
the internal clock and then outputs it as an active-high signal.
This signal can also be used as a system reset signal.
.
- - ' ,
''.
-.,'.. .
-.
"
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4-9. READY (ready) ... Input . .
The basic bus cycle of the
~PD70208G
requires four
clocks~
How-
ever, when the READY sIgnal goes low Onactive) awailstate OW) is
inserted between T3 and-T4 states
and:thus-the
bus
cycle~is·ex­
tended. This function iS,used for merTidry or 1/0 whose acces_s.tim9 is
slow. .-
This signal is internally synchronized with the clock ar:ld,-supplied to
each block. Then ilis checked during T3 and TW states. .. '.'-
Other than by this signal, TW state can-be also-,inserted by-program-
mable wait functIon.
4-10.NMI (nOnmaSkableinterrupt) ... Input
This, pil)Jnputs. an
int~rrupt
requ,est_signaf
thatcanno~ be-·m·ask.~d
by
softWare. . ' . .
This input Signal is rising-edge'triggered and ,is:_s::tmpl,ed.in each' clock
cycle. When the current instruction has been executed, an interrupt
assigned with No.2 vector is generated. '
I
This interrupt is also used to release the standby mpde of the CPU.
4-11. MRD (memory read) ... 3-state output
This signal becomes active '(lbw'level) 'when data is'read from the
memory. This signal also becomes a91ive,
-""~hen
the memory is
refreshed by the on-chip refresh control unit or when data are trans-
ferred from the memory to I/O by the on-chip DMA control unit.
The MRD signal becomes active during T2, T3, and TWstates of the
bus cycle. '
This pin becomes high impedance during
h~ld'
acknowledge.
4-12. MWR (memory write) ... 3-stateoutp!lt
This signal becomes active (low level) when data are written to the
memory. This signal also becomes active when data are transferred
from the VO to memory by the on-chip DMA control uhit When data
are processed by the CPU, the
JiiIWR
signal becomes active durIng
T2, T3, and TW states. However, when dat" are processed
by
the
DMA unit, the
JiiIWR
signal becomes active during T3 and TW states.
This pin becomes high impedance during hold acknowledge.
4-13. lORD (I/O read) ... 3,state output
This signal becomes
~cthie
(lOW level) when- data are reac from the
I/O. However, if the I/O to be accessed is on the chip, it will not
become active. The lORD signal also becomes active when data are
transferred from the 110 to the memory by the on-chip DMA control
unit. This Signal becomes active du'ring T2; -13 and' TW states of the
bus cycle.
This pin becomes high impedance dLiring hold acknowledge.
4-14.IOWR (I/O write) ... 3-state output
This signal becomes active (lOW level) when data are written to the
110. However, if the 110 to be accessed is on the chip, it will not
become active. The
1OWR'
Signal also becomes active when data are
transferred from the memory to 110 by the on-Chip DMA control
un~.
This signal becomes active during T2, T3, and TW states when data
are processed by the CPU. However, when data are processed by
the DMAU, the
lOWJrt
signal becomes active during T3 and TW states
for normal write fiming; T2, T3, and TW states for extended wrfte
timing.
This pin becomes high impedance during hold acknowledge.
4-15. ASTB (address strobe) .,. Output
This signal is an active-high strobe signal that externally latches ad-
dress information. This signal becomes active while the dock
(CLKOUT) in T1 state of the bus cycle is at low level.
This pin outputs low-level signal during hold acknowledge.