Texas Instruments OMAP-L137 User Manual page 137

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Table 6-63. Additional
No.
Required delay from SPI0_SCS asserted at slave to first
25 t
d(SCSL_SPC)S
SPI0_CLK edge at slave.
Required delay from final SPI0_CLK
26 t edge before SPI0_SCS is
d(SPC_SCSH)S
deasserted.
Delay from master asserting SPI0_SCS to slave driving
27 t
ena(SCSL_SOMI)S
SPI0_SOMI valid
Delay from master deasserting SPI0_SCS to slave 3-stating
28 t
dis(SCSH_SOMI)S
SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving
29 t
ena(SCSL_ENA)S
SPI0_ENA valid
Delay from final clock receive edge
30 t on SPI0_CLK to slave 3-stating or
dis(SPC_ENA)S
driving high SPI0_ENA.
(1) These parameters are in addition to the general timings for SPI slave modes
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is 3-
stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
Table 6-64. General Timing Requirements for SPI1 Master Modes
No.
1 t Cycle Time, SPI1_CLK, All Master Modes
c(SPC)M
2 t Pulse Width High, SPI1_CLK, All Master Modes
w(SPCH)M
3 t Pulse Width Low, SPI1_CLK, All Master Modes
w(SPCL)M
Delay, initial data bit valid on
4 t SPI1_SIMO to initial edge on
d(SIMO_SPC)M
SPI1_CLK
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
Copyright © 2008–2014, Texas Instruments Incorporated
(1)
SPI0 Slave Timings, 5-Pin Option
PARAMATER
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
(4)
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
PARAMATER
Polarity = 0, Phase =
0,
to SPI1_CLK rising
Polarity = 0, Phase =
1,
to SPI1_CLK rising
Polarity = 1, Phase =
(2)
0,
to SPI1_CLK falling
Polarity = 1, Phase =
1,
to SPI1_CLK falling
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SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
(2) (3)
MIN
0.5t
c(SPC)M
0.5t
c(SPC)M
(Table 6-57).
MIN
greater of 3P or 20 ns
0.5t
c(SPC)M
0.5t
c(SPC)M
Peripheral Information and Electrical Specifications
OMAP-L137
OMAP-L137
MAX UNIT
2P ns
+ P +
5
P + 5
ns
+ P +
5
P + 5
P + 18.5 ns
P + 18.5 ns
18.5 ns
2.5 P + 18.5
2.5 P + 18.5
ns
2.5 P + 18.5
2.5 P + 18.5
(1)
MAX UNIT
256P ns
- 1 ns
- 1 ns
5
- 0.5t + 5
c(SPC)M
ns
5
- 0.5t + 5
c(SPC)M
137