Mddr Controller Configuration; Mss Ddr Control Registers - Microsemi SmartFusion2 MSS Configuration Manual

2 – MDDR Controller Configuration
When you use the MSS DDR Controller to access an external DDR Memory, the DDR Controller must be
configured at runtime. This is done by writing configuration data to dedicated DDR controller
configuration registers. This configuration data is dependent on the characteristics of the external DDR
memory and your application. This section describes how to enter these configuration parameters in the
MSS DDR controller configurator and how the configuration data is managed as part of the overall
Peripheral Initialization solution.

MSS DDR Control Registers

The MSS DDR Controller has a set of registers that need to be configured at runtime. The configuration
values for these registers represent different parameters, such as DDR mode, PHY width, burst mode,
and ECC. For complete details about the DDR controller configuration registers, refer to the
SmartFusion2 SoC FPGA High Speed DDR Interfaces User's
MDDR Registers Configuration
Use the Memory Initialization
tabs to enter parameters that correspond to your DDR Memory and application. Values you enter in
these tabs are automatically translated to the appropriate register values. When you click a specific
parameter, its corresponding register is described in the Register Description pane (lower portion in
Figure 1-1 on page
Memory Initialization
The Memory Initialization tab allows you to configure the ways you want your LPDDR/DDR2/DDR3
memories initialized. The menu and options available in the Memory Initialization tab vary with the type of
DDR memory (LPDDR/DDR2/DDR3) you use.
Refer to your DDR Memory Data Sheet when you configure the options.
When you change or enter a value, the Register Description pane gives you the register name and
register value that is updated. Invalid values are flagged as warnings.
Figure 2-1, Figure
respectively.
(Figure 2-1, Figure
4).
2-2, and Figure 2-3 show the Initialization tab for LPDDR, DDR2 and DDR3,
Guide.
2-2, and Figure 2-3) and Memory Timing (Figure 2-4)
6