Mss Ddr Configuration Path - Microsemi SmartFusion2 MSS Configuration Manual

MSS DDR Configuration Path

The Peripheral Initialization solution requires that, in addition to specifying MSS DDR configuration
register values, you configure the APB configuration data path in the MSS (FIC_2). The SystemInit()
function writes the data to the MDDR configuration registers via the FIC_2 APB interface.
Note: If you are using System Builder the configuration path is set and connected automatically.
Figure 2-7 • FIC_2 Configurator Overview
To configure the FIC_2 interface:
1. Open the FIC_2 configurator dialog
2. Select the Initialize peripherals using Cortex-M3 option.
3. Make sure that the MSS DDR is checked, as are the Fabric DDR/SERDES blocks if you are using
them.
4. Click OK to save your settings. This will expose the FIC_2 configuration ports (Clock, Reset, and
APB bus interfaces), as shown in
5. Generate the MSS. The FIC_2 ports (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK and
FIC_2_APB_M_RESET_N) are now exposed at the MSS interface and can be connected to the
CoreConfigP and CoreResetP as per the Peripheral Initialization solution specification.
(Figure 2-7) from the MSS configurator.
Figure 2-8.
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