Port Description - Microsemi SmartFusion2 MSS Configuration Manual

3 – Port Description
DDR PHY Interface
Table 3-1 • DDR PHY Interface
Port Name
MDDR_CAS_N
MDDR_CKE
MDDR_CLK
MDDR_CLK_N
MDDR_CS_N
MDDR_ODT
MDDR_RAS_N
MDDR_RESET_N
MDDR_WE_N
MDDR_ADDR[15:0]
MDDR_BA[2:0]
MDDR_DM_RDQS ([3:0]/[1:0]/[0])
MDDR_DQS ([3:0]/[1:0]/[0])
MDDR_DQS_N ([3:0]/[1:0]/[0])
MDDR_DQ ([31:0]/[15:0]/[7:0])
MDDR_DQS_TMATCH_0_IN
Direction Description
OUT DRAM CASN
OUT DRAM CKE
OUT Clock, P side
OUT Clock, N side
OUT DRAM CSN
OUT DRAM ODT
OUT DRAM RASN
OUT DRAM Reset for DDR3
OUT DRAM WEN
OUT Dram Address bits
OUT Dram Bank Address
INOUT Dram Data Mask
INOUT Dram Data Strobe Input/Output
- P Side
INOUT Dram Data Strobe Input/Output
- N Side
INOUT DRAM Data Input/Output
IN FIFO in signal
Remarks
Ignore this signal for LPDDR
Interface. For LPDDR, mark
it unused.
Ignore this signal for LPDDR
Interface. For LPDDR, mark
it unused.
Address MSB vary with
the number of rows in the
DDR memory. See
Table 3‐2 below.
For LPDDR, BA[2] is not
used. Slice the bus and
mark BA[2] unused.
Connect BA[1:0] to
LPDDR.
For LPDDR interface, this
port direction is OUT. RDQS
function is not supported.
Only DM function is
supported. Connect it to
DRAM_DM input port of
LPDDR.
For LPDDR, connect this
signal to
FDDR_DQS_TMATCH_0_
OUT.
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