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3.1 Satellite Board Headers
All the interface connections between a satellite board and the Tegra 200 Series Developer Board are through two sets of
Samtec FTS series 50-pin Micro Strips connectors.
Table 2. Satellite Connectors Pinout
Dir
Pin #
Signal Name
In
1
KB_COL7
In
3
KB_COL6
In
5
KB_COL5
In
7
KB_COL4
In
9
KB_COL3
In
11
KB_COL2
In
13
KB_COL1
In
15
KB_COL0
Out
17
KB_ROW15
Out
19
KB_ROW14
Out
21
KB_ROW13
Out
23
KB_ROW12
Out
25
KB_ROW11
Out
27
KB_ROW10
Out
29
KB_ROW9
Out
31
KB_ROW8
Out
33
KB_ROW7
Out
35
KB_ROW6
Out
37
KB_ROW5
Out
39
KB_ROW4
Out
41
KB_ROW3
Out
43
KB_ROW2
Out
45
KB_ROW1
Out
47
KB_ROW0
In
49
EC_KSI0
DG-04927-001_v01
Signal Name
Pin #
Dir
EC_KSO17
2
Out
EC_KSO16
4
Out
EC_KSO15
6
Out
EC_KSO14
8
Out
EC_KSO13
10
Out
EC_KSO12
12
Out
EC_KSO11
14
Out
EC_KSO10
16
Out
EC_KSO9
18
Out
EC_KSO8
20
Out
EC_KSO7
22
Out
EC_KSO6
24
Out
EC_KSO5
26
Out
EC_KSO4
28
Out
EC_KSO3
30
Out
EC_KSO2
32
Out
EC_KSO1
34
Out
EC_KSO0
36
Out
EC_KSI7
38
In
EC_KSI6
40
In
EC_KSI5
42
In
EC_KSI4
44
In
EC_KSI3
46
In
EC_KSI2
48
In
EC_KSI1
50
In
Advance Information – Subject to Change
NVIDIA CONFIDENTIAL
Tegra 200 Series Developer Board User Guide
Dir
Pin #
Signal Name
Out
1
LED_WPAN*
Out
3
LED_WLAN*
Out
5
LED_WWAN*
In
7
W_DISABLE *
Out
9
LED_WIFI_BT *
Out
11
LED_CHARGE*
Out
13
LED_POWER*
Out
15
LED_SCROLL_LOCK*
Out
17
LED_CAPS_LOCK*
Out
19
LED_NUM_LOCK*
21
GND
In
23
SPDIF_IN
Out
25
SPDIF_OUT
27
GND
Out
29
IR_TXD
In
31
IR_RXD
In
33
LID_OPEN*
Out
35
VDD_5V0_MB
Out
37
VDD_5V0_MB
In
39
TP_IRQ*
In
41
TS_IRQ*
43
NO CONNECT
In
45
ONKEY*
In
47
FORCE_RECOVERY*
In
49
RESET*
Signal Name
Pin #
Dir
VDD_CELL_RMT
2
In
UART4_TXD
4
Out
VDDIO_NAND_MB
6
Out
UART4_RXD
8
In
UART4_CTS*
10
In
UART4_RTS*
12
Out
NO CONNECT
14
FORCE_ACOK
16
In
VDDIO_SYS_MB
18
Out
PWR_I2C_SCL
20
Bi
PWR_I2C_SDA
22
Bi
VDD_3V3_MB
24
Out
VDD_3V3_MB
26
Out
GND
28
PS2_TS_CLOCK
30
Bi
PS2_TS_DATA
32
Bi
GND
34
CAM_I2C_SDA
36
Bi
CAM_I2C_SCL
38
Bi
GND
40
PS2_TP_CLOCK
42
Bi
PS2_TP_DATA
44
Bi
LED_HEARTBEAT*
46
Out
SYS_RESET_B*
48
Out
VDD_3V3_EC_MB
50
Out
13
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