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Table 9. PCIe Pinout
Signal
PEX_CLK_OUT1_N
PEX_CLK_OUT1_P
PEX_CLK_OUT2_N
PEX_CLK_OUT2_P
PEX_L0_RXN
PEX_L0_RXP
PEX_L0_TXN
PEX_L0_TXP
PEX_L1_RXN
PEX_L1_RXP
4.6 Display
LCD Displays
HDMI
VGA (CRT)
SDTV / HDTV Out
4.6.1 LCD Displays
The Tegra 250 supports a broad range of interfaces for connecting to LCD displays. Two separate display controllers can drive
up to two displays. One of the displays can be an LCD while the other an HDMI display, standard NTSC/PAL TV or CRT.
Alternately, a number of dual LCD combinations are supported. An 18-bit interface to an external LVDS Transmitter to connect
to common Smartbook panels is described. Other interface options are possible. The example assumes an SPWG 18BPP
single channel LVDS panel interface.
Figure 15. Single Channel LVDS Signal Mapping
DG-04927-001_v01
Pin
Signal
AC4
PEX_L1_TXN
AD4
PEX_L1_TXP
Y4
PEX_L2_RXN
Y5
PEX_L2_RXP
AA5
PEX_L2_TXN
AA4
PEX_L2_TXP
AD1
PEX_L3_RXN
AD2
PEX_L3_RXP
AA7
PEX_L3_TXN
AA6
PEX_L3_TXP
Advance Information – Subject to Change
NVIDIA CONFIDENTIAL
Tegra 200 Series Developer Board User Guide
Pin
AC2
AC1
V4
V3
AA1
AA2
V6
V5
Y3
Y2
27
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