Efuse - Nvidia TEGRA DG-04927-001_V01 User Manual

Figure 24. Debug Interface Connection
AUDIO
1.8V VDDIO_AUDIO
UART
1.8V VDDIO_UART
SYSTEM
1.8V VDDIO_SYS
LCD
1.8V VDDIO_LCD
Unused Pins
If JTAG is not implemented, then JTAG_RTCK and JTAG_TDO can be left unconnected. The JTAG_TDI and JTAG_TMS pins
still need to be pulled up, and JTAG_TRST_N and JTAG_TCK must be pulled down. The rail the JTAG pins reside on
(VDDIO_SYS) must be powered for any mode including Deep Sleep.

4.9.3 EFUSE

The Tegra 250 design must provide a way to supply a 3.3V power source to the FUSE_SRC pin. This can be accomplished
using one of the following mechanisms:
Test point to connect external 3.3V supply
3.3V Output of on-board LDO controlled by the Tegra 250 GPIO
3.3V Output of PMU, controlled by PWR_I2C from the Tegra 250
Permanently connected to always-on 3.3V supply
The power source must provide a nominal voltage of 3.3V and be able to supply a minimum of 100mA. When not powered, a
10K Ω pull-down resistor each on FUSE_SRC is required. A 0.1uf bypass capacitor is also recommended on FUSE_SRC. The
KFUSE_SRC pin must be pulled down with a 10KΩ resistor only..
Figure 25. EFUSE Connections
DG-04927-001_v01
VDDIO_SYS
Tegra
SPI1_SCK
SPI1_CS0_N
SPI1_MOSI
SPI1_MISO
UART1_TXD
UART1_RXD
JTAG_RTCK
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N No Stuff
100KΩ
LCD_PWR1
Advance Information – Subject to Change
NVIDIA CONFIDENTIAL
Tegra 200 Series Developer Board User Guide
VDDIO_SYS
10KΩ
DEBUG
10KΩ
CONNECTOR
11
10
9
8
7
6
5
4
3
2
1
DBG_IRQ_N
ONKEY_N
12
13
14 DBG_RESET_N
15
16
17
18
19
20
21
22
36