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4.3 DRAM Memory Configurations
Tegra 250 supports standard DDR2 SDRAM. Up to 1GB total memory, two chip selects and two Clock Enables are supported.
A full 8-device configurations using x8 DDR2 devices is shown. A 4 device configuration is possible and is a subset of the 8
device configuration. Only Rank 0 would be used in this case.
4.3.1 Four, 8-bit DDR2 devices
Four Devices are routed in parallel to form single 32-bit memory Rank (1 Chip Select, 1 Clock Enable)
CLK+/-, Address, BA, RAS/CAS/WR, CKE0, CS0 and ODT0 are routed to all devices (4 loads)
DQ[31:0], DQS[3:0]+/-, DQM[3:0] are routed to one device each (1 load)
4.3.2 Eight, 8-bit DDR2 devices
Two Ranks of four devices each form two 32-bit memory Ranks (2 Chip Selects, 2 Clock Enables)
CLK+/-, Address, BA, RAS/CAS/WR and ODT0 are routed to all devices (8 loads)
CKE[1:0] and CS0[1:0]_N are routed to 4 devices each (4 loads)
DQ[31:0], DQS[3:0]+/-, DQM[3:0] are routed to 2 devices each (2 loads)
Figure 10. Eight, 8-bit DDR2 Configuration
DG-04927-001_v01
Advance Information – Subject to Change
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Tegra 200 Series Developer Board User Guide
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