Related Manuals for Nvidia TEGRA DG-04927-001_V01
Summary of Contents for Nvidia TEGRA DG-04927-001_V01
- Page 1 USER GUIDE ™ Tegra 200 Series Developer Board Advance Information – Subject to Change NVIDIA CONFIDENTIAL January 2010 | DG-04927-001_v01...
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Page 2: Document Change History
Document Change History Version Date JAN 22, 2010 Description Initial Release Advance Information – Subject to Change NVIDIA CONFIDENTIAL DG-04927-001_v01... -
Page 3: Table Of Contents
Table of Contents 1.0 INTRODUCTION ... 5 2.0 DEVELOPER BOARD OVERVIEW ... 6 2.1 Feature List ... 6 2.2 NVIDIA® Tegra™ 250 ... 8 2.3 System DRAM ... 8 2.4 Boot Device ... 8 2.5 LCD Interface ... 9 2.6 External Display Support ... 9 2.7 Audio ... - Page 4 4.9.4 Strapping Pins ... 37 5.0 THERMAL ... 38 5.1 Major Component Thermal Specifications ... 38 5.2 Thermal Considerations for Components ... 38 DG-04927-001_v01 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide ...
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Page 5: Introduction
Details a generic Smartbook Development System: development system consists of the NVIDIA Developer Kit plus a satellite board containing most of the user input devices and some features for test and development;... -
Page 6: Developer Board Overview
2.0 DEVELOPER BOARD OVERVIEW 2.1 Feature List Applications Processor NVIDIA Tegra 250, 23x23mm ,0.8mm pitch DRAM and Flash Memory 8, 128Mx8, DDR2 @ 333MHz TPS51116RGET DDR2 Buck Regulator Hynix 8-bit NAND on board Internal SD/MMC socket supports eMMC module Baseband... - Page 7 Force Rec Satellite Reset Headers Button Button Button (J16, J17) (S2) (S1) (S3) Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide PCIE WiFi Ant Mini- (J24) Card 0 (J27) (J19) PCIE Mini- Card 1...
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Page 8: Nvidia® Tegra™ 250
2.2 NVIDIA® Tegra™ 250 The NVIDIA Tegra 250 computer-on-a-chip is suited for handheld and mobile applications. It’s primary purpose is to control all system peripherals and provide computing power. Table 1 Features (Available / Used on Tegra 200 Series Developer Board) -
Page 9: Lcd Interface
USB3 (PHY) is routed to an SMSC LAN9514 USB Hub and Ethernet controller. This controller provides one Ethernet interface and four USB Host ports. The Tegra 200 Series Developer Board routes the Ethernet signals to a standard RJ-45 jack. Three DG-04927-001_v01 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide... -
Page 10: Storage
PCIe Mini-Card slot #1 (J28) could be used for other peripherals such as Solid-State drives or a different WiFi solution. Note: Contact NVIDIA for list of certified PCI express peripherals Advance Information – Subject to Change DG-04927-001_v01 NVIDIA CONFIDENTIAL... -
Page 11: User Interface
Main system 1.8V: Texas Instruments TPS51116RGER PCIe 1.05V for the Tegra 250: Texas Instruments TPS62290DRVR External LDOs 1.2V: Texas Instruments TPS72012YZUT 1.5V: Texas Instruments TPS74201RGWR DG-04927-001_v01 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide... -
Page 12: Satellite Board Headers
ONKEY Button PWR_I2C EEPROM Tx, Rx, RTS, CTS RF On/Off Switch 16x8 18x8 HeartBeat Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide Additional Functionality Coin Cell RESET Button PROG RS-232 TRCV LID_Status Switch... -
Page 13: Satellite Board Headers
W_DISABLE * LED_WIFI_BT * LED_CHARGE* LED_POWER* LED_SCROLL_LOCK* LED_CAPS_LOCK* LED_NUM_LOCK* VDD_5V0_MB VDD_5V0_MB NO CONNECT FORCE_RECOVERY* Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide Signal Name Pin # LED_WPAN* VDD_CELL_RMT LED_WLAN* UART4_TXD VDDIO_NAND_MB UART4_RXD UART4_CTS* UART4_RTS*... -
Page 14: I2C Map
WM8903 Audio Codec 1.8V ID EEPROM 1.8V ID EEPROM 1.8V Temperature Sensor Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide ID / I2C Addr Location Tegra 250 Slave addr: Main Board 0x45 0x28... -
Page 15: Connection Examples
Tegra 200 Series Developer Board User Guide 4.0 CONNECTION EXAMPLES 4.1 Power Figure 6. Tegra 250 Power Connection Example Advance Information – Subject to Change DG-04927-001_v01 NVIDIA CONFIDENTIAL... -
Page 16: Major Components
1.0V-1.2V nominal voltage range with 25mV steps CORE and RTC domains must track each other within 170mV Tracking can be ensured in software Optimized DVS handled by NVIDIA BSP (DVFS architecture) Turned off if CORE_PWR_REQ is de-asserted – on at 1.2V when CORE_PWR_REQ asserted CPU switcher 0.85-1.0V nominal voltage range with 25mV steps... -
Page 17: Power Supplies
1.05 TPS62290, DC/DC 2.7 – 3.6 2.85 PMU LD05 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide Enable PMU SM2 (3.7V) + Internal Trigger CORE_PWR_REQ + Internal Trigger CPU_PWR_REQ + Internal Trigger PMU SM2 (3.7V) + Internal Trigger PMU SM2 (3.7V) + Internal Trigger... -
Page 18: Power Sequencing
System clocks required before SYS_RESET_N goes high 2: Recommended Power-down sequence is reverse of Power-up. DG-04927-001_v01 32KHz Ramp Time Oscillator Ramp Time Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide BATTERY or AC/DC PMU SUPPLY EXTERNAL SUPPLY Signals... -
Page 19: Bypass Capacitor Recommendations
DG-04927-001_v01 4.7uF Bulk Power Rail Capacitors VDD_CPU AVDD_HDMI AVDD_USB_PLL AVDD_USB AVDD_IC_USB AVDD_PEX AVDD_PLLE VDDIO_DDR_RX VDDIO_VI VDDIO_SDIO VDDIO_SYS VDDIO_UART VDDIO_PEX_CLK Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide 0.1uF Bypass 4.7uF Bulk Capacitors Capacitors... -
Page 20: Clocks
Table 6 contains the requirements for the crystal used, the value of the parallel bias resistor and information to calculate the values of the two external load capacitors (C and C ) shown in the circuit. Advance Information – Subject to Change DG-04927-001_v01 NVIDIA CONFIDENTIAL... - Page 21 DG-04927-001_v01 ) can be found with formula C = [(C are typically of equal value, C = (C /2)+C Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide Unit ±50 MΩ Ω )/(C )]+C .
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Page 22: Dram Memory Configurations
CKE[1:0] and CS0[1:0]_N are routed to 4 devices each (4 loads) DQ[31:0], DQS[3:0]+/-, DQM[3:0] are routed to 2 devices each (2 loads) Figure 10. Eight, 8-bit DDR2 Configuration DG-04927-001_v01 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide... -
Page 23: Unused Pins
DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide... -
Page 24: Nand
USB Hub. An example of USB3 interfacing to an SMSC LAN9514 USB Hub and Ethernet controller is provided in section 3.7 . The IC_USB interface is used to connect to compatible SIM Cards. DG-04927-001_v01 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide... -
Page 25: Force Recovery
Figure 13 shows the Tegra 250 interfacing with an external ULPI-USB PHY. The USB PHY can be used to interface to a compatible Baseband, a USB Hub, etc. Figure 13. Example ULPI connection to External SMSC USB3317 USB PHY DG-04927-001_v01 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide... -
Page 26: Pcie
Solid-State drives or Wi-Fi may also take advantage of the high performance PCIe interfaces on the PCIe Mini Card connectors. Contact NVIDIA for a list of certified PCI express peripherals. Figure 14. Example LAN9514 USB/Ethernet Hub and Dual Mini-PCIe Connectors... -
Page 27: Display
Smartbook panels is described. Other interface options are possible. The example assumes an SPWG 18BPP single channel LVDS panel interface. Figure 15. Single Channel LVDS Signal Mapping DG-04927-001_v01 Signal PEX_L1_TXN PEX_L1_TXP PEX_L2_RXN PEX_L2_RXP PEX_L2_TXN PEX_L2_TXP PEX_L3_RXN PEX_L3_RXP PEX_L3_TXN PEX_L3_TXP Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide... - Page 28 LCD_D10 AA28 LCD_D20 LCD_D11 AA27 LCD_D21 LCD_D12 LCD_D22 LCD_D14 LCD_D23 LCD_D15 LCD_DE LCD_D16 LCD_HSYNC LCD_D17 LCD_PCLK LCD_D18 AB25 LCD_VSYNC AD26 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide AA23 AB23 AA22 AC22 AD27...
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Page 29: Hdmi
Any unused signal lines can be left unconnected. If HDMI is not implemented, AVDD_HDMI/HDMI_PLL rails and all signal pins can be left unconnected. DG-04927-001_v01 Signal AF17 HDMI_TXD1N AG17 HDMI_TXD1P AE16 HDMI_TXD2N AE17 HDMI_TXD2P Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide AC18 AD18 AH18 AG18... -
Page 30: Vga (Crt) Out
4.6.3.1 Unused Pins Any unused VDAC pins (VDAC_R, VDAC_G, VDAC_B) can be left unconnected. If the TV/CRT Output function will not be supported, AVDD_VDAC, VDAC_R/G/B, VDAC_RSET and VDAC_VREF should be left unconnected. Advance Information – Subject to Change DG-04927-001_v01 NVIDIA CONFIDENTIAL... -
Page 31: Camera
DSI_CSI_RUP, DSI_CSI_RND pins should be left unconnected. DG-04927-001_v01 Signal AH26 CSI_D2AP AG26 CSI_CLKBN AD20 CSI_CLKBP AE20 CSI_D1BN AH23 CSI_D1BP Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide AG23 AB20 AC20 AH24 AG24... -
Page 32: Sd/Sdio/Mmc
The SD/MMC socket uses the controller mapped to the SDIO2 controller pins on the VI interface domain. Figure 20. Tegra 200 Series Developer Board Reference design 4-bit SD/MMC Card Socket Connection Example Advance Information – Subject to Change DG-04927-001_v01 NVIDIA CONFIDENTIAL... -
Page 33: Emmc Device Connections
Not needed if eMMC or other device directly on-board 0.1uf eMMC Core (2.85V) Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide 0.1uf GND_EMI2 C_DETECT_N WP_N... -
Page 34: Sdio Device Connections
GPIO. If none of the signals are used on one of the digital power domains (except VDDIO_DDR and VDDIO_SYS which must be powered for normal operation), then the associated power rail can be left unconnected or tied to GND. Advance Information – Subject to Change DG-04927-001_v01 NVIDIA CONFIDENTIAL... -
Page 35: Miscellaneous
When used in the normal operating mode to access the internal CPUs, in order to reset the Tegra 250 JTAG block, a reset command is used rather than toggling the JTAG_TRST_N pin. DG-04927-001_v01 Signal THERMD_N THERMD_P Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide... -
Page 36: Efuse
KFUSE_SRC pin must be pulled down with a 10KΩ resistor only.. Figure 25. EFUSE Connections DG-04927-001_v01 VDDIO_SYS VDDIO_SYS 10KΩ 10KΩ SPI1_SCK JTAG_TDI No Stuff 100KΩ DBG_IRQ_N Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide ONKEY_N DEBUG CONNECTOR DBG_RESET_N... -
Page 37: Strapping Pins
00: Serial JTAG chain, MPCORE and AVP SW uses to determine which BCT table to use for DRAM, NAND timing Selects Boot device - depends on how Boot fuses are burned Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide... -
Page 38: Thermal
Operating Case Temperature Operating Case Temperature Operating Case temperature Operating Case Temperature Operating Case Temperature Operating Case Temperature Operating Case Temperature Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide Units Notes °C °C °C °C °C... - Page 39 Tegra 200 Series Developer Board User Guide Figure 27. Top View – Heat Generating and Thermal Sensitive Components Figure 28. Bottom View – Heat Generating and Thermal Sensitive Components Advance Information – Subject to Change DG-04927-001_v01 NVIDIA CONFIDENTIAL...
- Page 40 This could be an additional piece of metal, or having the case (bottom of PCB) or keyboard plate (top of PCB) contact the hotter components. Figure 29. Considerations for resolving for thermal “hot spots” DG-04927-001_v01 Advance Information – Subject to Change NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide...
- Page 41 NVIDIA Corporation. Macrovision Compliance Statement NVIDIA Products that are Macrovision enabled can only be sold or distributed to buyers with a valid and existing authorization from Macrovision to purchase and incorporate the device into buyer’s products. Macrovision copy protection technology is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698 and other intellectual property rights.
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