Block Diagram - Atmel AVR ATmega88PA Specification Sheet

2. Overview
2.1

Block Diagram

8161DS–AVR–10/09
The ATmega48PA/88PA/168PA/328P is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48PA/88PA/168PA/328P achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
ATmega48PA/88PA/168PA/328P
Watchdog
Power
Timer
Supervision
POR / BOD &
Watchdog
RESET
Oscillator
Oscillator
Flash
Circuits /
Clock
Generation
EEPROM
8bit T/C 0 16bit T/C 1
Analog
8bit T/C 2
Comp.
USART 0 SPI
PORT D (8) PORT B (8)
PD[0..7] PB[0..7]
debugWIRE
PROGRAM
LOGIC
SRAM
CPU
AVCC
AREF
GND
2
A/D Conv.
Internal
6
Bandgap
TWI
PORT C (7)
RESET
XTAL[1..2]
PC[0..6] ADC[6..7]
5