Instruction Set Summary - Atmel AVR ATmega88PA Specification Sheet

6. Instruction Set Summary

Mnemonics Operands
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr
ADC Rd, Rr
ADIW Rdl,K
SUB Rd, Rr
SUBI Rd, K
SBC Rd, Rr
SBCI Rd, K
SBIW Rdl,K
AND Rd, Rr
ANDI Rd, K
OR Rd, Rr
ORI Rd, K
EOR Rd, Rr
COM Rd
NEG Rd
SBR Rd,K
CBR Rd,K
INC Rd
DEC Rd
TST Rd
CLR Rd
SER Rd
MUL Rd, Rr
MULS Rd, Rr
MULSU Rd, Rr
FMUL Rd, Rr
FMULS Rd, Rr
FMULSU Rd, Rr
BRANCH INSTRUCTIONS
RJMP k
IJMP
(1)
JMP k
RCALL k
ICALL
(1)
CALL k
RET
RETI
CPSE Rd,Rr
CP Rd,Rr
CPC Rd,Rr
CPI Rd,K
SBRC Rr, b
SBRS Rr, b
SBIC P, b
SBIS P, b
BRBS s, k
BRBC s, k
BREQ k
BRNE k
BRCS k
BRCC k
BRSH k
BRLO k
BRMI k
BRPL k
BRGE k
BRLT k
BRHS k
BRHC k
BRTS k
BRTC k
BRVS k
BRVC k
8161DS–AVR–10/09
Description
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
Exclusive OR Registers
One's Complement
Two's Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Multiply Unsigned
Multiply Signed
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Relative Jump
Indirect Jump to (Z)
Direct Jump
Relative Subroutine Call
Indirect Call to (Z)
Direct Subroutine Call
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
ATmega48PA/88PA/168PA/328P
Operation
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
<< 1
R1:R0 ← (Rd x Rr)
<< 1
R1:R0 ← (Rd x Rr)
<< 1
R1:R0 ← (Rd x Rr)
PC ← PC + k + 1
PC ← Z
PC ← k
PC ← PC + k + 1
PC ← Z
PC ← k
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
Rd − Rr − C
Rd − K
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
Flags #Clocks
Z,C,N,V,H 1
Z,C,N,V,H 1
Z,C,N,V,S 2
Z,C,N,V,H 1
Z,C,N,V,H 1
Z,C,N,V,H 1
Z,C,N,V,H 1
Z,C,N,V,S 2
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,C,N,V 1
Z,C,N,V,H 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
None 1
Z,C 2
Z,C 2
Z,C 2
Z,C 2
Z,C 2
Z,C 2
None 2
None 2
None 3
None 3
None 3
None 4
None 4
I 4
None 1/2/3
Z, N,V,C,H 1
Z, N,V,C,H 1
Z, N,V,C,H 1
None 1/2/3
None 1/2/3
None 1/2/3
None 1/2/3
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
None 1/2
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