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Page 6
3
Setup and Configuration
The main functional blocks of the evaluation board are shown below.
SVT13T04 board
J3
Host
I/F
Power
JP2
Q1
J2
JP1
Figure 3-1 S5U13T04P00C100 Reference Board Block Diagram
CNF0 is configured with jumpers JP3 and JP4 as shown in the following table.
CNF0
S5U13T04P00C100 Evaluation Board User Manual
Revision 1.0
Reserved
For Testing
U1
S1D13T04
HVDD
CNF0
RVDD
JP3/JP4
Table 3-1 CNF0 Configuration Selection
JP3
JP4
0
Open
Short
H_RDY signal is all ways driven (Default)
1
Short
Open
H_RDY signal is open drain signal
Seiko Epson Corporation
J4
Comments
J1
Panel
2.0 Inch
I/F
EPD
Panel
XA3A-G-001-00
Issue Date: 2013/03/15
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