Texas Instruments TMS320C6711D User Manual page 75

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE/SDCAS/SSADS †
AOE/SDRAS/SSOE †
AWE/SDWE/SSWE †
† ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE/SDCAS/SSADS †
AOE/SDRAS/SSOE †
AWE/SDWE/SSWE †
† ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
FLOATING POINT DIGITAL SIGNAL PROCESSOR
1
2
BE1 BE2 BE3
4
EA
6
Q1
8
8
9
Figure 29. SBSRAM Read Timing
1
2
BE1 BE2
4
EA
10
Q1 Q2
8 8
12
Figure 30. SBSRAM Write Timing
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
1
3
BE4
5
7
Q2 Q3
1
3
BE3 BE4
5
11
Q3 Q4
12
TMS320C6711D
Q4
9
75