Figure 6-11 Dma Time Slot Allocation - Commodore Amiga Hardware Reference Manual

DMA Time Slot Allocation/Horizontal line
Decimal numbers above the Illustrations represent I~·resolutlon
cycles. Decimal n:Jmbers below the .lIustratlons represent hIgh·
resolution
cyeies.
Negative numbers
mdlc'lte
the sian of data
felch for dIsplays that afe larger than normal.
DeCImal numbers Inside the Illustrations represent the bit-plane
for which the data IS being fetched.
$10
~_.M~;MC'RY
REFRESH
--+ .....
OIS;K OMA TIME .... t4--A'UOIIO
OMATIME
Data fetch start can only be speCified at even
multiples of 8 clocks. ThiS
15
the clock poSition
which should be speCified for the normal Width
display.
120
word fetch for
320
pixel,
40
word
fetch for 640 pUlel Width)
Five clocks must occur before the data fetched for a particular
position can appear on·screen. For example, It data fetch start
tS $38, data will not be avatlable for display until clock number
$45. It IS available at $45 because display processing does not
begin until all of the btt·planes for a particular pixel have been
fetched.
• These operations only take slots If the associated operation is being performed.
Note Copper Data Move instructions reQuITe 4 slots.
Copper Walt instructions reQUire 6 slots.
#
ThiS cycle 0 appears to exclude one of the memory refresh cycles. This IS not the case.
Actual system hardware demands certain speCtflc values for data fetch start and display start.
Therefore thiS timing chart has been "adjusted" to match those reQuirements.
S Indicates a hex number.
Hardware stop Installed here. Data fetch cannot begm a"y sooner
than cycle $18. ThiS allows the user to wipe oul most of the sprites
.f deSired (by defmlng an extra'Wlde displayl bulleaves the audiO
and disk DMA untouched.
520
as cycle 7
D
320 mode Bit·PlaneOMA. by plane ..
• 640 mode Blt·Plane DMA. by plane ..
D
Slots available
fOf
Blltter. Copper and 68000 •
[I
Sprite OMA t (2words/channeU
Figure 6-11: DMA Time Slot Allocation
Some spntes are unusable It the display starts early due 10
an extra wardls) assocIated wllh a WIde display and Of
hOrizontal scrolling. In thiS case, the blt·plane DMA sleals
the cycles normally allocated to the sprites. as Illustrated
above.
A hardware data· fetch stop has been Inslalled at count SDa
so as to prevent the bit· plane data· fetch from overrunning
the time allotted for the memory refresh or disk OMA.
mID
AudiO DMA t (2 bytes/channel)
~
DlskDMA*
~
Memory Refresh
End of
HorIZontal
Line Data
Fetch Cycle