Rectangular Or Linear Address Scanning; Blitter Logic Operations - Commodore Amiga Hardware Reference Manual

Rectangular or Linear Address Scanning
The BLTSIZE register is written to define the horizontal and vertical size of a rectangu-
lar region of memory. The pointer register (BLTxPTx) specifies where in memory the
corresponding data block starts. The blitter adds (in ascending mode) or subtracts (in
descending mode) 2 from the pointer register for each 16-bit word transferred until the
count of "horizontal" words in the BLTSIZE register is met. Then it adds the contents
of the modulo register (BLTxMOD) to the pointer register. The value in the modulo
register thus represents the value to be added to the pointer register to get it from the
point in memory just past the end of a horizontal line to the beginning of the next hor-
izontalline of the rectangular region.
The blitter can be used to process linear rather than rectangular regions by setting the
horizontal or vertical count in BLTSIZE to
1.
Blitter Logic Operations
Three sources (A, B, and C) are available to the blitter logic unit. These sources are
usually one bit-plane from each of three separate graphics images. While each of these
sources is a rectangular region composed of many points, the same logic operation will be
performed on each point throughout the rectangular region. Accordingly, for purposes
of defining the blitter logic operation it is only necessary to describe what happens for all
of the possible combinations of one bit from each of the three sources. Therefore, there
are only eight possible data combinations (minterms). For each of these input possibili-
ties you need to specify whether the corresponding D (destination) output bit is on or
off. This information is collected in a standard format, the LF control byte in the
BLTCONO register, shown below. This byte programs the blitter to perform one of the
256 possible logic operations on three sources for a given blit.
For example, an LF control byte of $80 (
=
1000 0000 binary) turns on bits only for
those points of the D destination rectangle where the corresponding bits of A, B, and C
sources were all on (ABC
=
1, bit 7 of LF on). All other points in the rectangle, which
correspond to other combinations for A, B, and C, will be O. This is because bits 6
through 0 of the LF control word, which specify the D output for these situations, are
set to O. The following paragraphs discuss two conceptual approaches to designing this
LF control byte. One approach uses logic equations; the other uses Venn diagrams.
Blitter Hardware 171