Digilent Genesys Reference Manual page 10

Genesys Reference Manual
The DDR2 interface follows the pinout and routing guidelines specified in the Xilinx Memory Interface
Generator (MIG) User Guide. The interface supports SSTL18 signaling, and all address, data, clocks,
and control signals are delay-matched and impedance-controlled. Address and control signals are
terminated through 47-ohm resistors to a 0.9V V
(ODT) feature of the SODIMM. Two well-matched DDR2 clock signal pairs are provided to the
SODIMM that can be driven with low-skew clocks from the FPGA.
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H30
E31
K29
G31
J30
R31
L29
Virtex 5
J29
F31
F30
See Table
, and data signals use the On-Die-Termination
TT
x14
RAS#
CAS#
WE#
BA0
BA1
BA2
S0#
SODIMM
S1#
ODT0
ODT1
14
AD[13:0]
64
DQ[63:0]
16
DS[7:0] (differential)
8
DM[7:0]
2
I2C (SDA, SCK)
6
Clocks (differential)
DDR2
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