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Figure 7–1 DEC 4000 AXP System Architecture
Serial Control Bus
Serial Control Bus
TM
Data
d i
i g t a l
Tal k
SD R D C D T R SI
SCHOLAR
Plus
Indicates Optional
Power Subsystem
Front
Power
End
System
DC5
DC3
Unit
Contr
CPU 0
Operator
Control
Panel
Ethernet Port 0
Ethernet Port 1
Asynchronous Serial Line
T es t
Off
Loop
On
(with modem control)
Asynchronous Serial Line
(Console Line)
Futurebus+ Option 6
Futurebus+ Option 5
Futurebus+ Option 4
Futurebus+ Option 3
Futurebus+ Option 2
Futurebus+ Option 1
Subsystems and Components
To Outlet
Memory 2
CPU 1
Memory 1
Memory 0
64, 128 MB
System Bus
DSSI/SCSI Bus A
DSSI/SCSI Bus B
I/O
DSSI/SCSI Bus C
Module
DSSI/SCSI Bus D
SCSI Only Bus E
(Removable Media)
Futurebus+
Learning More About Your System 7–5
Memory 3
MLO-009365
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