Circuit Description; Camera System - Sony CBK-HD01 Maintenance Manual

1-2. Circuit Description

1-2-1. Camera System

AT-177 board
The AT-177 board is the microprocessor board that
controls the camera block.
1. Microprocessor peripherals
The CPU (IC209) uses SH2A (R5S7206), and the clock pro-
vides 32 MHz from an external source that is six multiplica-
tion in the CPU so that the clock runs on 192 MHz. The mem-
ory is composed of 64 MBit flash memory (IC302, IC303), 16
MBit SRAM (IC3056), and 1 MBit FRAM (IC308).
2. A/D input of the CPU
The A/D port equipped to the CPU is connected to the
following signal lines and monitored: CC position, ND
position, temperature, IRIS position of a camera lens,
ZOOM position, and mic volume level.
3. Internal communication
The serial communication includes intercommunication
with the BleConSh IC on the DCP-44 board, the writing
controls to the character generator IC, and
intercommunication with the disc.
The parallel communication is equipped with the 8-bit data
line, the total 11-bit address line (A0-A7, A14-A16),
control line clock, XRD, XWR, OE, DIR, CS, and
(QWERTY, ZXCV, TG).
In addition, the intercommunication is performed with
EEPROM on the DCP-44 board, the DAC and I/O port IC
for the video signal, and the I/O port IC on the FP-157
board with the I2C line that is installed directly to the CPU.
4. Memory stick circuit
The memory stick controller IC (IC610) is driven at 16
MHz, and the two-way communication and the clock
signal are directly connected from the connector (CN602)
to the memory stick connector of the MS-86 board via the
coaxial harness. This is compatible with the Memory Stick
PRO/DUO.
5. External communication
The 2 channel serial communication driver CXD9093R
(IC411) is equipped and performs external communication
with the remote control unit RM-B150/B750.
6. ROM jig connector (CN601)
The connector CN101 that can be connected to the jig for
writing the boot program (MS-86 board) is included.
1-4
DCP-44 board
The DCP-44 board consists of the block for A/D conversion
of the analog RGB signal from the PA-342/PA-342A/PA-
343/PA-343A/PA-344 board via the feedback clamp circuit,
the cam-era DSP block that performs the signal processing,
the dri-ver block that sends the analog signal that is D/A con-
vert-ed to the outputs, and the I/F block to the AT-177 board.
After passing through the pre-filter (FL300 to FL302), the
analog RGB signal input from the PA-342/PA-342A/PA-
343/PA-343A/PA-344 board is converted to 74 MHz rate
14-bit digital RGB sign-al by the A/D converter (IC107 to
IC109), then input into the camera processor IC (IC600).
The camera signal processor IC (IC600) detects the
average value and the peak value of the camera video
signals that are required for the AUTO operations of the
camera such as AUTO black balance, AUTO white
balance, and AUTO iris control. The detected average
value and peak value are sent to the AT-microprocessor on
the AT-177 board. In addition to the above operations, the
25/30 PsF conversion function and the 1080 to 720
conversion function are realized by using the DDR
SDRAM (IC700 to 704).
After passing through white balance, white shading, and
flare correction, the camera main video signal performs the
Digital GAIN UP, then performs the Digital Noise
Reduction. Then, the matrix signal and the detail signal are
added to perform pedestal control, gamma correction, knee
correction, and white clip processing. After passing
through the selector circuit with which either the camera
main video signal or the color bar signal can be selected,
the selected signal is output from IC (IC600) to IC800.
The digital VBS signal and the digital Y signal for VF
supplied from the camera signal processor IC (IC800) are
converted into the analog VBS signal and analog VF signal
by the D/A converter* (IC1513, IC1524, IC1525). After
passing through the circuit with which either the camera
analog VBS signal or the VF Y can be selected, the
selected signal is output to the TEST OUT connector.
After passing through the circuit with which either the
GENLOCK IN connector input or the video signal can be
selected, the selected signal is output to the VF connector.
In addition, the sync separation circuit and the PLL circuit
to synchronize with the external input video of the GEN-
LOCK IN connector are included.
The detected average value of the video signal detected in
the camera signal processor IC (IC600) and peak value are
loaded to the AT-microprocessor on the AT-177 board
through the 8-bit data bus.
PDW-700/V1 (E)