Siemens SIMATIC S7-200 System Manual page 196

S7-200 Programmable Controller System Manual
Use the following equation to compute the address of the most significant bit of the Shift Register
(MSB.b):
MSB.b = [(Byte of S_BIT) + ([N] - - 1 + (bit of S_BIT)) / 8].[remainder of the division by 8]
For example: if S_BIT is V33.4 and N is 14, the
following calculation shows that the MSB.b is V35.1.
MSB.b
On a Shift Minus, indicated by a negative value of
length (N), the input data shifts into the most
significant bit of the Shift Register, and shifts out of
the least significant bit (S_BIT). The data shifted out
is then placed in the overflow memory bit (SM1.1).
On a Shift Plus, indicated by a positive value of
length (N), the input data (DATA) shifts into the least
significant bit of the Shift Register, specified by the
S_BIT, and out of the most significant bit of the Shift
Register. The data shifted out is then placed in the
overflow memory bit (SM1.1).
The maximum length of the shift register is 64 bits,
positive or negative. Figure 6-35 shows bit shifting g
for negative and positive values of N. f ti d
Example: Shift Register Bit Instruction
Timing Diagram
I0.2
Positive
transition (P)
I0.3
First shift
182
= V33 + ([14] -- 1 +4)/8
= V33 + 17/8
= V33 + 2 with a remainder of 1
= V35.1
g
iti l f N
Second shift
Shift Minus,
Length = - -14
V33
V34
V35
Shift Plus,
Length = 14
V33
V34
V35
g
Figure 6-35 Shift Register Entry and Exit
Network 1
LD I0.2
EU
SHRB I0.3, V100.0, +4
7 (MSB)
Before V100
first shift
Overflow (SM1.1)
After V100
first shift
Overflow (SM1.1)
After V100
second
shift
Overflow (SM1.1)
S_BIT
MSB LSB
4
7 0
7 0
7 1 0
MSB of Shift Register
S_BIT
MSB LSB
4
7 0
7 0
7 1 0
MSB of Shift Register
0 (LSB)
S_BIT
I0.3
0 1 0 1
x
S_BIT
I0.3
1 0 1 1
0
S_BIT
I0.3
0 1 1 0
1