Siemens SIMATIC S7-200 System Manual page 171

The pulse train output interrupts provide immediate notification of completion of outputting the
prescribed number of pulses. A typical use of pulse train outputs is stepper motor control.
You can enable each of the above interrupts by attaching an interrupt routine to the related I/O
event.
Time-Based Interrupts
Time-based interrupts include timed interrupts and the timer T32/T96 interrupts. You can specify
actions to be taken on a cyclic basis using a timed interrupt. The cycle time is set in 1-ms
increments from 1 ms to 255 ms. You must write the cycle time in SMB34 for timed interrupt 0, and
in SMB35 for timed interrupt 1.
The timed interrupt event transfers control to the appropriate interrupt routine each time the timer
expires. Typically, you use timed interrupts to control the sampling of analog inputs or to execute a
PID loop at regular intervals.
A timed interrupt is enabled and timing begins when you attach an interrupt routine to a timed
interrupt event. During the attachment, the system captures the cycle time value, so subsequent
changes to SMB34 and SMB35 do not affect the cycle time. To change the cycle time, you must
modify the cycle time value, and then re-attach the interrupt routine to the timed interrupt event.
When the re-attachment occurs, the timed interrupt function clears any accumulated time from the
previous attachment and begins timing with the new value.
After being enabled, the timed interrupt runs continuously, executing the attached interrupt routine
on each expiration of the specified time interval. If you exit RUN mode or detach the timed
interrupt, the timed interrupt is disabled. If the global disable interrupt instruction is executed, timed
interrupts continue to occur. Each occurrence of the timed interrupt is queued (until either
interrupts are enabled or the queue is full).
The timer T32/T96 interrupts allow timely response to the completion of a specified time interval.
These interrupts are only supported for the 1-ms resolution on-delay (TON) and off-delay (TOF)
timers T32 and T96. The T32 and T96 timers otherwise behave normally. Once the interrupt is
enabled, the attached interrupt routine is executed when the active timer's current value becomes
equal to the preset time value during the normal 1-ms timer update performed in the S7-200. You
enable these interrupts by attaching an interrupt routine to the T32/T96 interrupt events.
Interrupt Priority and Queuing
Interrupts are serviced by the S7-200 on a first-come-first-served basis within their respective
priority group. Only one user-interrupt routine is ever being executed at any point in time. Once the
execution of an interrupt routine begins, the routine is executed to completion. It cannot be
pre-empted by another interrupt routine, even by a higher priority routine. Interrupts that occur
while another interrupt is being processed are queued for later processing.
Table 6-48 shows the three interrupt queues and the maximum number of interrupts they can
store.
Table 6-48 Maximum Number of Entries per Interrupt Queue
Queue
Communications queue
I/O Interrupt queue
Timed Interrupt queue
Potentially, more interrupts can occur than the queue can hold. Therefore, queue overflow
memory bits (identifying the type of interrupt events that have been lost) are maintained by the
system. Table 6-49 shows the interrupt queue overflow bits. You should use these bits only in an
interrupt routine because they are reset when the queue is emptied, and control is returned to the
main program.
S7-200 Instruction Set
CPU 221, CPU 222, CPU 224
4
16
8
Chapter 6
CPU 224XP and CPU 226
8
16
8
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