Advanced Chipset Features - DFI-ITOX LT600-DR User Manual

3
BIOS Setup

Advanced Chipset Features

x CAS Latency Time
x DRAM RAS# to CAS# Delay
x DRAM RAS# Precharge
x Precharge Delay <tRAS>
x System Memory Frequency
↑↓→←
F5: Previous Values
The settings on the screen are for reference only. Your version may not be
identical to this one.
This section gives you functions to configure the system based on
the specific features of the chipset. The chipset manages bus speeds
and access to system memory resources.
be altered unless necessary.
because they provide the best operating conditions for your system.
The only time you might consider making any changes would be if
you discovered some incompatibility or that data was being lost
while using your system.
DRAM Timing Selectable
This field is used to select the timing of the DRAM.
68
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Timing Selectable
SLP_S4# Assertion Width
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
PCI Express Root Port Func
** VGA Setting **
PEG/Onchip VGA Control
On-Chip Frame Buffer Size
DVMT Mode
DVMT/FIXED Memory Size
Boot Display
: Move Enter: Select
By SPD The EEPROM on a DIMM has SPD (Serial Pres-
ence Detect) data structure that stores informa-
tion about the module such as the memory type,
memory size, memory speed, etc. When this op-
tion is selected, the system will run according to
the information in the EEPROM. This option is the
default setting because it provides the most sta-
ble condition for the system. The "CAS Latency
Time" to "Precharge Delay" fields will show the
default settings by SPD.
Advanced Chipset Features
By SPD
Auto
Auto
Auto
Auto
Auto
4 to 5 Sec.
Enabled
Disabled
Disabled
Press Enter
Auto
8MB
DVMT
128MB
Auto
+/-/PU/PD: Value F10: Save
F6: Fail-Safe Defaults
These items should not
The default settings have been chosen
Item Help
Menu Level
ESC: Exit F1: General Help
F7: Optimized Defaults