Advanced Chipset Features - DFI-ITOX SR100-N User Manual

Dfi-itox sr100-n system board user's manual
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3
BIOS Setup

Advanced Chipset Features

↑↓→←
F5: Previous Values
The settings on the screen are for reference only. Your version may not be
identical to this one.
This section gives you functions to configure the system based on
the specific features of the chipset. The chipset manages bus speeds
and access to system memory resources.
be altered unless necessary.
because they provide the best operating conditions for your system.
The only time you might consider making any changes would be if
you discovered some incompatibility or that data was being lost
while using your system.
System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM ad-
dressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
70
Phoenix - AwardBIOS CMOS Setup Utility
System BIOS Cacheable
** VGA Setting **
On-Chip Frame Buffer Size
DVMT Mode
DVMT/FIXED Memory Size
Boot Display
Panel Number
: Move
Enter: Select
Advanced Chipset Features
Enabled
8MB
DVMT
128MB
Auto
03.1024 x 768 18 Bit
+/-/PU/PD: Value
F10: Save
F6: Fail-Safe Defaults
These items should not
The default settings have been chosen
Item Help
Menu Level
ESC: Exit
F1: General Help
F7: Optimized Defaults

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