Muratec F-110 Field Engineering Manual page 55

Circuit Description
ECP HARDWARE HANDSHAKING TIMING (REVERSE)
nACK
nAUTOFD
PPD ( 7: 0)
BUSY
nINI T
PE
1. The host request a reverse channel transfer by setting nINIT low
2. The peripheral signals that it is OK to proceed by setting PE low
3. The peripheral places data on the data lines and indicates a data cycle by setting BUSY high
4. Peripheral asserts nACK low to indicate valid data
5. Host acknowledges by setting nAUTOFD high
6. Peripheral sets nACK high. This is the edge that should be used to clock the data into the host
7. Host sets nAUTOFD low to indicate that it is ready for the next byte
8. The cycle repeats, but this time it is a command cycle because BUSY is low
4-22
1 2 3 4 5 6
BYTE0
DATA BYTE
7 8
BYTE1
COM M AND BYTE