Muratec F-110 Field Engineering Manual page 39

Circuit Description
Signal
nECS[1:0]
nRCS[2]
nRCS[1]/GOPA[7]
nRCS[0]
SC_CONPHA/
GOPA[19]
SC_CONPHB/
GOPA[20]
SC_CUR[3:0]
PWMO[2:0]/
GOPA[13:11]
VDO2/GOPA[29]
VDO1/GOPA[14]
LSU_CLK/
GOPA[15]
nHSYNC1/GIP[10]
nLREADY/GIP[11]
nHSYNC2/GIP[12]
VDI/GIP[13]
VCLK/GIP[14]
nEXTWAIT/GIP[7]
RTCXIN
RTCXOUT
SLED[2:0]/
GOPA[18:16]
GAVRT
GAIN[2:0]
RTC_VDD
4-6
Pin No. I/O Type
12,13 O1
51 O2
50 O1
49 O1
102 O1
105 O1
103, 104,
O1
106, 107
118~120 O1
121 O4
122 O5
123 O1
125 I1
126 I1
127 I1
128 I2
129 I2
130 I3
202 I7
203 O7
196~198 O1
205 I5
206~208 I5
201
Not external chip select. Three I/O banks are provided for
external memory-mapped I/O operations. Each I/O bank
contains up to 4M half-word. The nECS signals indicate that
an external I/O bank is selected.
Not ROM/SRAM chip select. The KS32C65100 can access
up to three external ROM/SRAM banks. nRCS[0]
corresponds to ROM/SRAM bank 0, nRCS[1] to bank 1, and
nRCS[2] to bank 2. By controlling the nRCS signals, CPU
addresses can be mapped into the physical memory banks.
Scan motor control/Bi-phase
Scan motor control/Bi-phase
Scan motor bi-current/uni-phase
PWM out signal
Video out from PIFC
Video out from LSU control
Clock for LSU motor
HSYNC1
LSU ready
HSYNC2
Video data input from RET
External video clock
External wait
RTC oscillator clock input.
RTC oscillator clock output.
CIS LED signals
Top reference voltage for general ADC
Analog inputs for general ADC
RTC VDD.
Description