Muratec F-110 Field Engineering Manual page 37

Circuit Description
Signal
CIS_CLK
CIS_SI
PHA_IA0
PHA_IA1
PHB_IB0
PHB_IB1
LF_PH0/GOPA[21]
LF_PH1/GOPA[22]
CR_PHA/GOPA[23]
CR_PHB/GOPA[24]
CRIA0/GOPA[25]
CRIA1/GOPA[26]
CRIB0/GOPA[27]
CRIB1/GOPA[28]
CHX/GIP[8]
CHY/GIP[9]
ADDR[21:0]
DATA[15:0]
nRAS[1:0]
nCAS[1:0]
nOE
nWE
nPHGA[13:1]/
GOPB[12:0]
PHOE[16:1]/
GIOP[26:11]
4-4
Pin No. I/O Type
6 O1
7 O1
164 O1
165 O1
167 O1
168 O1
163 O1
166 O1
110 O1
113 O1
109 O1
111 O1
112 O1
114 O1
116 I3
117 I3
77~80,
82~88,
O5
90~100
59~66,
I/O3
68~75
52,53 O1
54,55 O1
56 O1
57 O6
16~24,
O1
26~29
31~38,
I/O1
40~47
CIS shift clock
CIS latch signal
Line feed motor phase signal A
Line feed motor phase signal AZ
Line feed motor phase signal B
Line feed motor phase signal BZ
Line feed motor control signal 0
Line feed motor control signal 1
Direction control line for phase A
Direction control line for phase B
Current control line 0 for phase A
Current control line 1 for phase A
Current control line 0 for phase B
Current control line 1 for phase B
Encode sensor
Encode sensor
Address bus. The 22bit address bus, ADDR[21:0], covers
the full 4M half-words address range of each ROM/SRAM,
DRAM, and external I/O bank
External bi-directional 16-bit data bus.
Not row address strobe for DRAM. The KS32C65100
supports up to two DRAM banks. One nRAS output is
provided for each bank.
Not column address strobe for DRAM. The two nCAS
outputs indicate the byte selections whenever a DRAM bank
is accessed.
Not output enable. Whenever a memory access occurs, the
nOE output controls the output enable port of the specific
memory device.
Not write enable. Whenever a memory access occurs, the
nWE output controls the write enable port of the specific
memory device.
Gate control line for print head.
Drain control line for print head.
Description