7.2.14.2 LSSD_MODE ............................................................................................................. 275
7.2.14.3 L1_TSTCLK ................................................................................................................ 276
7.2.14.4 L2_TSTCLK ................................................................................................................ 276
7.2.14.5 BVSEL ........................................................................................................................ 276
7.2.15 Clock Signals ..................................................................................................................... 276
8.1 Bus Interface Overview ................................................................................................................. 280
8.1.3 Bus Signal Clocking ............................................................................................................. 282
8.1.5 Direct-Store Accesses ......................................................................................................... 283
8.2 Memory-Access Protocol .............................................................................................................. 284
8.2.1 Arbitration Signals ............................................................................................................... 285
8.2.2 Miss-under-Miss .................................................................................................................. 286
8.3 Address-Bus Tenure ..................................................................................................................... 290
8.3.2 Address Transfer ................................................................................................................. 292
8.3.2.1 Address-Bus Parity ....................................................................................................... 294
8.4 Data-Bus Tenure ........................................................................................................................... 301
8.4.1 Data-Bus Arbitration ............................................................................................................ 301
8.4.2 Data-Bus Write-Only ............................................................................................................ 303
8.4.3 Data Transfer ....................................................................................................................... 303
8.5 Timing Examples ........................................................................................................................... 309
8.6.1 32-Bit Data Bus Mode ......................................................................................................... 316
750gx_umTOC.fm.(1.2)
March 27, 2006
IBM PowerPC 750GX and 750GL RISC Microprocessor
User's Manual
Page 9 of 377