Effect Of Alignment In Data Transfers; Table 8-3. Burst Ordering-32-Bit Bus; Table 8-4. Aligned Data Transfers - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Table 8-3. Burst Ordering—32-Bit Bus
Data Transfer
First data beat
Second data beat
Third data beat
Fourth data beat
Fifth data beat
Sixth data beat
Seventh data beat
Eighth data beat
Note:
A[29–31] are always 0b000 for burst transfers by the 750GX.
"U" and "L" represent the upper and lower word of the double word respectively.

8.3.2.4 Effect of Alignment in Data Transfers

Table 8-4 lists the aligned transfers that can occur on the 750GX bus. These are transfers in which the data
is aligned to an address that is an integral multiple of the size of the data. For example, Table 8-4 shows that
1-byte data is always aligned. However, for a 4-byte word to be aligned, it must be oriented on an address
that is a multiple of four.

Table 8-4. Aligned Data Transfers

Transfer Size TSIZ0
0
0
0
0
Byte
0
0
0
0
0
0
Half word
0
0
Note: The entries with an "x" indicate the byte portions of the requested operand that are read or written during a bus transaction.
The entries with a "–" are not required and are ignored during read transactions, and they are driven with undefined data during all write
transactions.
Bus Interface Operation
Page 296 of 377
A[27–28] = 00 A[27–28] = 01
DW0-U DW1-U
DW0-L DW1-L
DW1-U DW2-U
DW1-L DW2-L
DW2-U DW3-U
DW2-L DW3-L
DW3-U DW0-U
DW3-L DW0-L
(Page 1 of 2)
TSIZ1 TSIZ2 A[29–31]
0 1 000
0 1 001
0 1 010
0 1 011
0 1 100
0 1 101
0 1 110
0 1 111
1 0 000
1 0 010
1 0 100
1 0 110
For Starting Address:
A[27–28] = 10
DW2-U
DW2-L
DW3-U
DW3-L
DW0-U
DW0-L
DW1-U
DW1-L
Data-Bus Byte Lane(s)
0 1 2 3
x — — —
— x — —
— — x —
— — — x
— — — —
— — — —
— — — —
— — — —
x x — —
— — x x
— — — —
— — — —
A[27–28] = 11
DW3-U
DW3-L
DW0-U
DW0-L
DW1-U
DW1-L
DW2-U
DW2-L
4 5 6 7
— — — —
— — — —
— — — —
— — — —
x — — —
— x — —
— — x —
— — — x
— — — —
— — — —
x x — —
— — x x
gx_08.fm.(1.2)
March 27, 2006