Figure 6-5. Instruction Timing-Cache Hit - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Figure 6-5. Instruction Timing—Cache Hit
1
0
•••
0 add
1 fadd
2 add
3 fadd
4 b
5 fsub
Instruction
Queue
3 5
2 4
1 3
0 2
Completion
Queue
1
0
Instruction Timing
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2 3 4
6 fadd
7 fadd
8 add
9 add
10 add
11 add
12 fadd
14 fadd
11
10 12
9 11
7 8 10
6 7 9
8
7
3 6 6
2 3 3
1 2 2
0 1 1
5 6 7
13 add
14
13 (16)
12 14 (15)
11 13 14
10 12 13
9 11 12
10 11
8 9 10
7 8 9
6 7 8
3 6 7
8 9 10
Fetch (in IQ)
In dispatch entry (IQ0/IQ1)
Execute
Complete (In CQ)
In retirement entry (CQ0/CQ1)
(17)
(16) (18)
(15) (17)
14 (16)
13 (15)
12 14
11 13 14
10 12 13
9 11 12
gx_06.fm.(1.2)
March 27, 2006
11
14
13
12