IBM PowerPC 750GX User Manual page 375

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Stall, definition 211
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Static branch prediction 216
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stwcx. 162
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Superscalar, definition 211
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sync 162
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SYNC operation 143
Synchronization
context/execution synchronization
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execution of rfi 161
memory synchronization instructions
SYSCLK (system clock) signal
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System call exception 171
System linkage instructions
System register unit
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execution timing 234
latency, CR logical instructions
latency, system register instructions
T
TA (transfer acknowledge) signal
Table search flow (primary and secondary)
TBL/TBU (time base lower and upper) registers
TBST (transfer burst) signal
TEA (transfer error acknowledge) signal
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Termination 300 303
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Thermal assist unit (TAU)
Thermal management interrupt exception
THRMn (thermal management) registers
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Throughput, definition 211
Timing diagrams, interface
address transfer signals
burst transfers with data delays
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single-beat reads 310
single-beat reads with data delays
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single-beat writes 311
single-beat writes with data delays
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use of TEA 315
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using DBWO 320
Timing, instruction
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BPU execution timing 225
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branch timing example
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cache hit 220
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cache miss 223
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execution unit 225
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FPU execution timing 232
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instruction dispatch 224
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instruction flow 215
instruction scheduling guidelines
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IU execution timing 232
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latency summary 238
load/store unit execution timing
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SRU execution timing
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stage, definition 211
TLB
750gx_umIX.fm.(1.2)
March 27, 2006
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90
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IBM PowerPC 750GX and 750GL RISC Microprocessor
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description 199
invalidate (tlbie instruction)
LRU replacement
organization for ITLB and DTLB
TLB miss and table search operation
TLB invalidate
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description 201
TLB management instructions
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TLB miss, effect
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tlbie 120
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tlbsync 120
Transactions, data cache
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Transfer 292 303
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Trap instructions
TS (transfer start) signal
TSIZn (transfer size) signals
TTn (transfer type) signals
U, V, W
UMMCR0 (user monitor mode control register 0)
UMMCR1 (user monitor mode control register 1)
62 UPMCn (user performance monitor counter) registers
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75 354
Use of TEA, timing
User instruction set architecture (UISA)
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description 41
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registers 59
USIA (user sampled instruction address) register
355
Using DBWO, timing
Virtual environment architecture (VEA)
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WIMG bits 308
Write-back, definition
Write-through mode (W bit)
cache interactions
Write-with-Atomic operation
Write-with-Flush operation
Write-with-Kill operation
WT (write-through) signal
X
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XER register 59
User's Manual
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Index