Data-Bus Parity (Dp[0-7]); Table 7-5. Dp[0-7] Signal Assignments - IBM PowerPC 750GX User Manual

Data Bus (DH[0–31], DL[0–31])—Output
State Asserted/
Negated
Timing Assertion/
Negation
High
Impedance
Data Bus (DH[0–31], DL[0–31])—Input
State Asserted/
Negated
Timing Assertion/
Negation
7.2.7.2 Data-Bus Parity (DP[0–7])
The eight data-bus parity (DP[0–7]) signals are both input and output signals.
Data-Bus Parity (DP[0–7])—Output
State Asserted/
Negated
Timing Assertion/
Negation/
High
Impedance
Table 7-5. DP[0–7] Signal Assignments
Signal Name
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
gx_07.fm.(1.2)
March 27, 2006
Represents the state of data during a data write. For single-beat (cache
inhibited or write through) writes, byte lanes not selected for data transfer will
not supply valid data (no data mirroring).
First or only beat begins on the cycle of DBB assertion and, for bursts, tran-
sitions on the cycle following each initially qualified assertion of TA.
Occurs on the bus clock cycle after the final assertion of TA, following the
assertion of TEA, or in certain ARTRY cases.
Represents the state of data during a data read transaction.
Data must be valid on the same bus clock cycle that TA is asserted, even if
during the last assertion cycle of DRTRY.
Represents odd parity for each of the 8 bytes of data write transactions. Odd
parity means that an odd number of bits, including the parity bit, are driven
high. The generation of parity is enabled through HID0. The signal assign-
ments are listed in Table 7-5.
The same as DL[0–31].
Signal Assignments
DH[0–7]
DH[8–15]
DH[16–23]
DH[24–31]
DL[0–7]
DL[8–15]
DL[16–23]
DL[24–31]
IBM PowerPC 750GX and 750GL RISC Microprocessor
User's Manual
Signal Descriptions
Page 267 of 377