IBM PowerPC 750GX User Manual page 372

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
,
integer 99
byte reverse instructions
,
floating-point move
,
floating-point store 104
,
integer load 99
,
integer multiple 102
,
integer store 101
memory synchronization
,
string instructions 103
memory control instructions
memory synchronization instructions
processor control instructions
,
reserved instructions 89
,
rfi 161
,
stwcx. 162
support for lwarx/stwcx.
,
sync 162
system linkage instructions
,
tlbie 120
,
tlbsync 120
,
trap instructions 108
Integer arithmetic instructions
Integer compare instructions
,
Integer load instructions 99
,
Integer logical instructions
Integer rotate/shift instructions
,
Integer store gathering 234
,
Integer store instructions
Integer unit execution timing
,
Interrupt, external 169
,
ISI exception 169
isync, instruction synchronization
,
ITLB organization 200
,
Kill block operation 143
L
L2CR (L2 cache control register)
Latency
,
load/store instructions
,
Latency, definition 210
Load/store
,
address generation 99
byte reverse instructions
,
execution timing 233
floating-point load instructions
floating-point move instructions
floating-point store instructions
integer load instructions
integer store instructions
latency, load/store instructions
load/store multiple instructions
,
string instructions 103
Logical address translation
,
LR (link register) 59
Index
Page 372 of 377
,
102
98
, ,
113 114
, ,
115 119
, ,
113 114
, , ,
108 113 118
,
319
,
108
,
92
,
93
94
,
95
101
,
232
, ,
115 162
, ,
81 329
244
,
102
,
104
,
98
,
105
,
99
,
101
,
244
,
102
,
179
,
lwarx/stwcx. support 319
M
,
Machine check exception
MCP (machine check interrupt) signal
MEI protocol
hardware considerations
,
read operations 140
,
state transitions 147
,
Memory accesses 282
Memory coherency bit (M bit)
,
cache interactions 125
,
timing considerations 235
Memory control instructions
, ,
description 115 119
Memory management unit
address translation flow
address translation mechanisms
block address translation
block diagrams
32-bit implementations
,
DMMU 185
,
IMMU 184
,
exceptions summary 192
,
features summary 180
implementation-specific features
instructions and registers
,
memory protection 187
,
overview 179
page address translation
,
page history status 188
,
real addressing mode
,
segment model 196
Memory synchronization instructions
,
Misaligned data transfer 299
Misalignment
,
misaligned accesses 82
MMCRn (monitor mode control registers)
MSR (machine state register)
,
FE0/FE1 bits 160
,
IP bit 163
,
PM bit 60
,
RI bit 161
settings due to exception
,
Multiple-precision shifts 95
N
,
No-DRTRY mode 318
167
, , ,
62 152 271
,
128
,
189
, ,
186 189
, , ,
186 189 196
,
183
,
180
,
194
, , ,
186 189 202
, –
196 199
,
189 195
, ,
113 114
, , ,
72 172
,
162
750gx_umIX.fm.(1.2)
March 27, 2006
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